2021-05-26 23:26:44 +02:00
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use core::mem;
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2022-06-12 22:15:44 +02:00
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2022-04-02 04:35:06 +02:00
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use defmt::{info, unwrap};
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2022-08-17 23:40:16 +02:00
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use embassy_executor::Spawner;
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2023-03-05 02:55:00 +01:00
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use embassy_nrf::qspi::Frequency;
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2023-03-05 21:37:21 +01:00
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use embassy_nrf::{bind_interrupts, peripherals, qspi};
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2022-08-17 23:40:16 +02:00
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use embassy_time::{Duration, Timer};
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2022-06-12 22:15:44 +02:00
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use {defmt_rtt as _, panic_probe as _};
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2021-05-26 23:26:44 +02:00
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// Workaround for alignment requirements.
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// Nicer API will probably come in the future.
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#[repr(C, align(4))]
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struct AlignedBuf([u8; 64]);
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2023-03-05 21:37:21 +01:00
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bind_interrupts!(struct Irqs {
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QSPI => qspi::InterruptHandler<peripherals::QSPI>;
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});
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2022-07-29 21:58:35 +02:00
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#[embassy_executor::main]
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2022-08-17 18:49:55 +02:00
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async fn main(_p: Spawner) {
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let mut p = embassy_nrf::init(Default::default());
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2021-05-26 23:26:44 +02:00
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loop {
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2021-05-27 00:42:46 +02:00
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// Config for the MX25R64 present in the nRF52840 DK
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2021-05-26 23:26:44 +02:00
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let mut config = qspi::Config::default();
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2023-03-05 02:55:00 +01:00
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config.capacity = 8 * 1024 * 1024; // 8 MB
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config.frequency = Frequency::M32;
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2021-05-27 00:42:46 +02:00
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config.read_opcode = qspi::ReadOpcode::READ4IO;
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config.write_opcode = qspi::WriteOpcode::PP4IO;
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config.write_page_size = qspi::WritePageSize::_256BYTES;
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2021-05-26 23:26:44 +02:00
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config.deep_power_down = Some(qspi::DeepPowerDownConfig {
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enter_time: 3, // tDP = 30uS
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exit_time: 3, // tRDP = 35uS
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});
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2023-03-05 02:33:02 +01:00
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let mut q = qspi::Qspi::new(
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2021-05-26 23:26:44 +02:00
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&mut p.QSPI,
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2023-03-05 21:37:21 +01:00
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Irqs,
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2021-05-26 23:26:44 +02:00
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&mut p.P0_19,
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&mut p.P0_17,
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&mut p.P0_20,
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&mut p.P0_21,
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&mut p.P0_22,
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&mut p.P0_23,
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config,
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2022-04-19 14:39:59 +02:00
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);
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2021-05-26 23:26:44 +02:00
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let mut id = [1; 3];
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2021-07-31 17:51:40 +02:00
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unwrap!(q.custom_instruction(0x9F, &[], &mut id).await);
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2021-05-26 23:26:44 +02:00
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info!("id: {}", id);
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// Read status register
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let mut status = [4; 1];
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2021-07-31 17:51:40 +02:00
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unwrap!(q.custom_instruction(0x05, &[], &mut status).await);
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2021-05-26 23:26:44 +02:00
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info!("status: {:?}", status[0]);
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if status[0] & 0x40 == 0 {
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status[0] |= 0x40;
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2021-07-31 17:51:40 +02:00
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unwrap!(q.custom_instruction(0x01, &status, &mut []).await);
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2021-05-26 23:26:44 +02:00
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info!("enabled quad in status");
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}
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let mut buf = AlignedBuf([0u8; 64]);
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info!("reading...");
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2021-07-31 17:51:40 +02:00
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unwrap!(q.read(0, &mut buf.0).await);
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2021-05-26 23:26:44 +02:00
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info!("read: {=[u8]:x}", buf.0);
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// Drop the QSPI instance. This disables the peripehral and deconfigures the pins.
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// This clears the borrow on the singletons, so they can now be used again.
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mem::drop(q);
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// Sleep for 1 second. The executor ensures the core sleeps with a WFE when it has nothing to do.
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// During this sleep, the nRF chip should only use ~3uA
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Timer::after(Duration::from_secs(1)).await;
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}
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}
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