2023-05-30 00:10:36 +02:00
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// required-features: ble
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2023-05-04 00:36:31 +02:00
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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2023-05-30 00:10:36 +02:00
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#[path = "../common.rs"]
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mod common;
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2023-05-04 00:36:31 +02:00
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2023-05-30 00:10:36 +02:00
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use common::*;
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2023-05-04 00:36:31 +02:00
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use embassy_executor::Spawner;
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2023-06-17 19:00:33 +02:00
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use embassy_futures::poll_once;
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2023-06-12 15:44:30 +02:00
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use embassy_stm32::bind_interrupts;
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2023-06-17 19:00:33 +02:00
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use embassy_stm32::ipcc::{Config, ReceiveInterruptHandler, TransmitInterruptHandler};
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2023-06-17 03:15:03 +02:00
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use embassy_stm32_wpan::ble::Ble;
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2023-06-16 04:02:10 +02:00
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use embassy_stm32_wpan::sys::Sys;
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2023-06-17 19:00:33 +02:00
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use embassy_stm32_wpan::{mm, TlMbox};
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2023-05-04 00:36:31 +02:00
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use embassy_time::{Duration, Timer};
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2023-05-26 11:03:01 +02:00
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bind_interrupts!(struct Irqs{
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2023-06-17 19:00:33 +02:00
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IPCC_C1_RX => ReceiveInterruptHandler;
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IPCC_C1_TX => TransmitInterruptHandler;
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2023-05-26 11:03:01 +02:00
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});
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2023-06-17 19:00:33 +02:00
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#[embassy_executor::task]
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async fn run_mm_queue() {
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mm::MemoryManager::run_queue().await;
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}
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2023-05-04 00:36:31 +02:00
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#[embassy_executor::main]
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2023-06-17 19:00:33 +02:00
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async fn main(spawner: Spawner) {
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2023-05-27 22:05:50 +02:00
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let p = embassy_stm32::init(config());
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2023-05-04 00:36:31 +02:00
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info!("Hello World!");
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2023-06-17 19:00:33 +02:00
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spawner.spawn(run_mm_queue()).unwrap();
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2023-05-04 00:36:31 +02:00
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let config = Config::default();
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2023-06-12 15:44:30 +02:00
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let mbox = TlMbox::init(p.IPCC, Irqs, config);
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2023-05-04 00:36:31 +02:00
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2023-06-17 19:00:33 +02:00
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let mut rx_buf = [0u8; 500];
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let ready_event = Sys::read().await;
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let _ = poll_once(Sys::read()); // clear rx not
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ready_event.write(&mut rx_buf).unwrap();
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info!("coprocessor ready {}", rx_buf);
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2023-05-04 00:36:31 +02:00
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loop {
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let wireless_fw_info = mbox.wireless_fw_info();
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match wireless_fw_info {
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2023-05-22 03:18:26 +02:00
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None => {}
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2023-05-04 00:36:31 +02:00
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Some(fw_info) => {
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let version_major = fw_info.version_major();
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let version_minor = fw_info.version_minor();
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let subversion = fw_info.subversion();
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let sram2a_size = fw_info.sram2a_size();
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let sram2b_size = fw_info.sram2b_size();
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info!(
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"version {}.{}.{} - SRAM2a {} - SRAM2b {}",
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version_major, version_minor, subversion, sram2a_size, sram2b_size
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);
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break;
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}
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}
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2023-05-22 03:18:26 +02:00
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Timer::after(Duration::from_millis(50)).await;
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2023-05-04 00:36:31 +02:00
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}
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2023-06-17 19:00:33 +02:00
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Sys::shci_c2_ble_init(Default::default()).await;
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2023-06-14 00:12:34 +02:00
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2023-06-17 19:00:33 +02:00
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info!("starting ble...");
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Ble::write(0x0c, &[]).await;
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2023-06-16 04:02:10 +02:00
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2023-06-17 19:00:33 +02:00
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info!("waiting for ble...");
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let ble_event = Ble::read().await;
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ble_event.write(&mut rx_buf).unwrap();
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2023-06-17 03:15:03 +02:00
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2023-06-17 19:00:33 +02:00
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info!("ble event: {}", rx_buf);
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2023-06-13 04:23:42 +02:00
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2023-06-17 19:00:33 +02:00
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// Timer::after(Duration::from_secs(3)).await;
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2023-05-04 00:36:31 +02:00
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info!("Test OK");
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cortex_m::asm::bkpt();
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}
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