2023-04-22 21:26:40 +02:00
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use core::ops::Div;
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#[allow(unused_imports)]
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use crate::pac::rcc;
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use crate::time::Hertz;
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/// Voltage Scale
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///
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/// Represents the voltage range feeding the CPU core. The maximum core
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/// clock frequency depends on this value.
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///
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/// Scale0 represents the highest voltage range
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#[derive(Copy, Clone, PartialEq)]
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pub enum VoltageScale {
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Scale0,
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Scale1,
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#[cfg(not(any(rcc_wl5, rcc_wle)))]
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Scale2,
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#[cfg(not(any(rcc_wl5, rcc_wle)))]
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Scale3,
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}
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/// AHB prescaler
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#[derive(Clone, Copy, PartialEq)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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Div3,
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Div4,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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Div5,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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Div6,
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Div8,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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Div10,
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Div16,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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Div32,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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impl Div<AHBPrescaler> for Hertz {
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type Output = Hertz;
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fn div(self, rhs: AHBPrescaler) -> Self::Output {
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let divisor = match rhs {
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AHBPrescaler::NotDivided => 1,
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AHBPrescaler::Div2 => 2,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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AHBPrescaler::Div3 => 3,
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AHBPrescaler::Div4 => 4,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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AHBPrescaler::Div5 => 5,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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AHBPrescaler::Div6 => 6,
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AHBPrescaler::Div8 => 8,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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AHBPrescaler::Div10 => 10,
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AHBPrescaler::Div16 => 16,
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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AHBPrescaler::Div32 => 32,
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AHBPrescaler::Div64 => 64,
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AHBPrescaler::Div128 => 128,
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AHBPrescaler::Div256 => 256,
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AHBPrescaler::Div512 => 512,
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};
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Hertz(self.0 / divisor)
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}
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}
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#[cfg(not(any(rcc_g4, rcc_wb, rcc_wl5, rcc_wle)))]
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impl From<AHBPrescaler> for rcc::vals::Hpre {
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fn from(val: AHBPrescaler) -> rcc::vals::Hpre {
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use rcc::vals::Hpre;
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match val {
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AHBPrescaler::NotDivided => Hpre::DIV1,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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impl From<AHBPrescaler> for u8 {
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fn from(val: AHBPrescaler) -> u8 {
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match val {
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AHBPrescaler::NotDivided => 0x0,
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AHBPrescaler::Div2 => 0x08,
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AHBPrescaler::Div3 => 0x01,
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AHBPrescaler::Div4 => 0x09,
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AHBPrescaler::Div5 => 0x02,
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AHBPrescaler::Div6 => 0x05,
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AHBPrescaler::Div8 => 0x0a,
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AHBPrescaler::Div10 => 0x06,
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AHBPrescaler::Div16 => 0x0b,
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AHBPrescaler::Div32 => 0x07,
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AHBPrescaler::Div64 => 0x0c,
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AHBPrescaler::Div128 => 0x0d,
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AHBPrescaler::Div256 => 0x0e,
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AHBPrescaler::Div512 => 0x0f,
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}
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}
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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impl Div<APBPrescaler> for Hertz {
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type Output = Hertz;
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fn div(self, rhs: APBPrescaler) -> Self::Output {
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let divisor = match rhs {
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APBPrescaler::NotDivided => 1,
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APBPrescaler::Div2 => 2,
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APBPrescaler::Div4 => 4,
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APBPrescaler::Div8 => 8,
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APBPrescaler::Div16 => 16,
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};
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Hertz(self.0 / divisor)
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}
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}
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2023-07-30 17:18:54 +02:00
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#[cfg(not(any(rcc_f1, rcc_f100, rcc_f1cl, rcc_g4, rcc_h7, rcc_h7ab, rcc_wb, rcc_wl5, rcc_wle)))]
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2023-04-22 21:26:40 +02:00
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impl From<APBPrescaler> for rcc::vals::Ppre {
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fn from(val: APBPrescaler) -> rcc::vals::Ppre {
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use rcc::vals::Ppre;
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match val {
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APBPrescaler::NotDivided => Ppre::DIV1,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
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impl From<APBPrescaler> for u8 {
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fn from(val: APBPrescaler) -> u8 {
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match val {
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APBPrescaler::NotDivided => 1,
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APBPrescaler::Div2 => 0x04,
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APBPrescaler::Div4 => 0x05,
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APBPrescaler::Div8 => 0x06,
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APBPrescaler::Div16 => 0x07,
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}
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}
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}
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