embassy/embassy-stm32/src/dma/gpdma.rs

357 lines
9.6 KiB
Rust
Raw Normal View History

2023-04-17 00:04:54 +02:00
#![macro_use]
use core::future::Future;
use core::pin::Pin;
use core::sync::atomic::{fence, Ordering};
2023-04-17 00:04:54 +02:00
use core::task::{Context, Poll};
2023-04-17 00:04:54 +02:00
use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use super::word::{Word, WordSize};
use super::Dir;
use crate::_generated::GPDMA_CHANNEL_COUNT;
2023-06-08 18:07:44 +02:00
use crate::interrupt::typelevel::Interrupt;
use crate::interrupt::Priority;
2023-04-17 00:04:54 +02:00
use crate::pac;
use crate::pac::gpdma::vals;
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[non_exhaustive]
pub struct TransferOptions {}
impl Default for TransferOptions {
fn default() -> Self {
Self {}
}
}
impl From<WordSize> for vals::ChTr1Dw {
fn from(raw: WordSize) -> Self {
match raw {
WordSize::OneByte => Self::BYTE,
WordSize::TwoBytes => Self::HALFWORD,
WordSize::FourBytes => Self::WORD,
}
}
}
struct State {
2023-04-17 00:04:54 +02:00
ch_wakers: [AtomicWaker; GPDMA_CHANNEL_COUNT],
}
impl State {
const fn new() -> Self {
2023-04-17 00:04:54 +02:00
const AW: AtomicWaker = AtomicWaker::new();
Self {
2023-04-17 00:04:54 +02:00
ch_wakers: [AW; GPDMA_CHANNEL_COUNT],
}
}
}
static STATE: State = State::new();
/// safety: must be called only once
2023-04-17 00:04:54 +02:00
pub(crate) unsafe fn init(irq_priority: Priority) {
foreach_interrupt! {
($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
crate::interrupt::typelevel::$irq::set_priority(irq_priority);
crate::interrupt::typelevel::$irq::enable();
};
}
crate::_generated::init_gpdma();
}
foreach_dma_channel! {
($channel_peri:ident, $dma_peri:ident, gpdma, $channel_num:expr, $index:expr, $dmamux:tt) => {
2023-04-17 00:04:54 +02:00
impl sealed::Channel for crate::peripherals::$channel_peri {
fn regs(&self) -> pac::gpdma::Gpdma {
pac::$dma_peri
}
2023-04-17 00:04:54 +02:00
fn num(&self) -> usize {
$channel_num
}
2023-04-17 00:04:54 +02:00
fn index(&self) -> usize {
$index
}
2023-04-17 00:04:54 +02:00
fn on_irq() {
unsafe { on_irq_inner(pac::$dma_peri, $channel_num, $index) }
}
2023-04-17 00:04:54 +02:00
}
2023-04-17 00:04:54 +02:00
impl Channel for crate::peripherals::$channel_peri {}
};
}
2023-04-17 00:04:54 +02:00
/// Safety: Must be called with a matching set of parameters for a valid dma channel
pub(crate) unsafe fn on_irq_inner(dma: pac::gpdma::Gpdma, channel_num: usize, index: usize) {
let ch = dma.ch(channel_num);
let sr = ch.sr().read();
2023-04-17 00:04:54 +02:00
if sr.dtef() {
panic!(
"DMA: data transfer error on DMA@{:08x} channel {}",
2023-06-19 03:07:26 +02:00
dma.as_ptr() as u32,
channel_num
2023-04-17 00:04:54 +02:00
);
}
if sr.usef() {
panic!(
"DMA: user settings error on DMA@{:08x} channel {}",
2023-06-19 03:07:26 +02:00
dma.as_ptr() as u32,
channel_num
2023-04-17 00:04:54 +02:00
);
}
2023-04-17 00:04:54 +02:00
if sr.suspf() || sr.tcf() {
// disable all xxIEs to prevent the irq from firing again.
ch.cr().write(|_| {});
2023-04-17 00:04:54 +02:00
// Wake the future. It'll look at tcf and see it's set.
STATE.ch_wakers[index].wake();
}
}
2023-04-17 00:04:54 +02:00
pub type Request = u8;
2023-04-17 00:04:54 +02:00
#[cfg(dmamux)]
pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static + super::dmamux::MuxChannel {}
#[cfg(not(dmamux))]
pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static {}
2023-04-17 00:04:54 +02:00
pub(crate) mod sealed {
use super::*;
pub trait Channel {
fn regs(&self) -> pac::gpdma::Gpdma;
fn num(&self) -> usize;
fn index(&self) -> usize;
fn on_irq();
}
}
2023-04-17 00:04:54 +02:00
#[must_use = "futures do nothing unless you `.await` or poll them"]
pub struct Transfer<'a, C: Channel> {
channel: PeripheralRef<'a, C>,
}
2023-04-17 00:04:54 +02:00
impl<'a, C: Channel> Transfer<'a, C> {
pub unsafe fn new_read<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
peri_addr: *mut W,
buf: &'a mut [W],
options: TransferOptions,
) -> Self {
Self::new_read_raw(channel, request, peri_addr, buf, options)
}
2023-04-17 00:04:54 +02:00
pub unsafe fn new_read_raw<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
peri_addr: *mut W,
buf: *mut [W],
options: TransferOptions,
) -> Self {
into_ref!(channel);
let (ptr, len) = super::slice_ptr_parts_mut(buf);
assert!(len > 0 && len <= 0xFFFF);
Self::new_inner(
channel,
request,
Dir::PeripheralToMemory,
peri_addr as *const u32,
ptr as *mut u32,
len,
true,
W::size(),
2023-04-17 00:04:54 +02:00
options,
)
}
pub unsafe fn new_write<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
buf: &'a [W],
peri_addr: *mut W,
options: TransferOptions,
) -> Self {
Self::new_write_raw(channel, request, buf, peri_addr, options)
}
pub unsafe fn new_write_raw<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
buf: *const [W],
peri_addr: *mut W,
options: TransferOptions,
) -> Self {
into_ref!(channel);
let (ptr, len) = super::slice_ptr_parts(buf);
assert!(len > 0 && len <= 0xFFFF);
Self::new_inner(
channel,
request,
Dir::MemoryToPeripheral,
peri_addr as *const u32,
ptr as *mut u32,
len,
true,
W::size(),
2023-04-17 00:04:54 +02:00
options,
)
}
pub unsafe fn new_write_repeated<W: Word>(
channel: impl Peripheral<P = C> + 'a,
request: Request,
repeated: &'a W,
count: usize,
peri_addr: *mut W,
options: TransferOptions,
) -> Self {
into_ref!(channel);
Self::new_inner(
channel,
request,
Dir::MemoryToPeripheral,
peri_addr as *const u32,
repeated as *const W as *mut u32,
count,
false,
W::size(),
2023-04-17 00:04:54 +02:00
options,
)
}
unsafe fn new_inner(
channel: PeripheralRef<'a, C>,
request: Request,
dir: Dir,
peri_addr: *const u32,
mem_addr: *mut u32,
mem_len: usize,
incr_mem: bool,
data_size: WordSize,
2023-04-17 00:04:54 +02:00
_options: TransferOptions,
) -> Self {
let ch = channel.regs().ch(channel.num());
2023-02-18 00:35:35 +01:00
// "Preceding reads and writes cannot be moved past subsequent writes."
fence(Ordering::SeqCst);
2023-04-17 00:04:54 +02:00
let this = Self { channel };
2023-04-17 00:04:54 +02:00
#[cfg(dmamux)]
super::dmamux::configure_dmamux(&mut *this.channel, request);
2023-04-17 00:04:54 +02:00
ch.cr().write(|w| w.set_reset(true));
ch.fcr().write(|w| w.0 = 0xFFFF_FFFF); // clear all irqs
ch.llr().write(|_| {}); // no linked list
ch.tr1().write(|w| {
w.set_sdw(data_size.into());
w.set_ddw(data_size.into());
w.set_sinc(dir == Dir::MemoryToPeripheral && incr_mem);
w.set_dinc(dir == Dir::PeripheralToMemory && incr_mem);
});
ch.tr2().write(|w| {
w.set_dreq(match dir {
Dir::MemoryToPeripheral => vals::ChTr2Dreq::DESTINATIONPERIPHERAL,
Dir::PeripheralToMemory => vals::ChTr2Dreq::SOURCEPERIPHERAL,
});
w.set_reqsel(request);
});
ch.br1().write(|w| {
// BNDT is specified as bytes, not as number of transfers.
w.set_bndt((mem_len * data_size.bytes()) as u16)
});
match dir {
Dir::MemoryToPeripheral => {
ch.sar().write_value(mem_addr as _);
ch.dar().write_value(peri_addr as _);
}
Dir::PeripheralToMemory => {
ch.sar().write_value(peri_addr as _);
ch.dar().write_value(mem_addr as _);
}
}
ch.cr().write(|w| {
// Enable interrupts
w.set_tcie(true);
w.set_useie(true);
w.set_dteie(true);
w.set_suspie(true);
// Start it
w.set_en(true);
});
2023-04-17 00:04:54 +02:00
this
}
2023-04-17 00:04:54 +02:00
pub fn request_stop(&mut self) {
let ch = self.channel.regs().ch(self.channel.num());
// Disable the channel. Keep the IEs enabled so the irqs still fire.
2023-06-19 03:07:26 +02:00
ch.cr().write(|w| {
w.set_tcie(true);
w.set_useie(true);
w.set_dteie(true);
w.set_suspie(true);
})
}
2023-04-17 00:04:54 +02:00
pub fn is_running(&mut self) -> bool {
let ch = self.channel.regs().ch(self.channel.num());
2023-06-19 03:07:26 +02:00
!ch.sr().read().tcf()
}
/// Gets the total remaining transfers for the channel
/// Note: this will be zero for transfers that completed without cancellation.
2023-04-17 00:04:54 +02:00
pub fn get_remaining_transfers(&self) -> u16 {
let ch = self.channel.regs().ch(self.channel.num());
2023-06-19 03:07:26 +02:00
ch.br1().read().bndt()
}
2023-04-17 00:04:54 +02:00
pub fn blocking_wait(mut self) {
while self.is_running() {}
2023-04-17 00:04:54 +02:00
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
fence(Ordering::SeqCst);
2023-04-17 00:04:54 +02:00
core::mem::forget(self);
}
}
2023-04-17 00:04:54 +02:00
impl<'a, C: Channel> Drop for Transfer<'a, C> {
fn drop(&mut self) {
self.request_stop();
while self.is_running() {}
// "Subsequent reads and writes cannot be moved ahead of preceding reads."
fence(Ordering::SeqCst);
}
}
2023-04-17 00:04:54 +02:00
impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
impl<'a, C: Channel> Future for Transfer<'a, C> {
type Output = ();
fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
STATE.ch_wakers[self.channel.index()].register(cx.waker());
2023-04-17 00:04:54 +02:00
if self.is_running() {
Poll::Pending
} else {
Poll::Ready(())
}
}
}