517 lines
17 KiB
Rust
517 lines
17 KiB
Rust
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#![macro_use]
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use core::future::poll_fn;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy_embedded_hal::SetConfig;
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use embassy_hal_common::{into_ref, PeripheralRef};
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pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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use crate::chip::FORCE_COPY_BUFFER_SIZE;
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
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use crate::interrupt::{Interrupt, InterruptExt};
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use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
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use crate::{pac, Peripheral};
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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TxBufferTooLong,
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RxBufferTooLong,
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/// EasyDMA can only read from data memory, read only buffers in flash will fail.
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DMABufferNotInDataMemory,
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}
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/// Interface for the SPIS peripheral using EasyDMA to offload the transmission and reception workload.
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///
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/// For more details about EasyDMA, consult the module documentation.
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pub struct Spis<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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#[non_exhaustive]
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pub struct Config {
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pub mode: Mode,
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pub orc: u8,
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pub def: u8,
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pub auto_acquire: bool,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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mode: MODE_0,
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orc: 0x00,
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def: 0x00,
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auto_acquire: true,
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}
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}
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}
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impl<'d, T: Instance> Spis<'d, T> {
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pub fn new(
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spis: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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cs: impl Peripheral<P = impl GpioPin> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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miso: impl Peripheral<P = impl GpioPin> + 'd,
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mosi: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(cs, sck, miso, mosi);
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Self::new_inner(
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spis,
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irq,
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cs.map_into(),
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sck.map_into(),
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Some(miso.map_into()),
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Some(mosi.map_into()),
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config,
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)
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}
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pub fn new_txonly(
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spis: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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cs: impl Peripheral<P = impl GpioPin> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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mosi: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(cs, sck, mosi);
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Self::new_inner(spis, irq, cs.map_into(), sck.map_into(), None, Some(mosi.map_into()), config)
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}
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pub fn new_rxonly(
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spis: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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cs: impl Peripheral<P = impl GpioPin> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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miso: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(cs, sck, miso);
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Self::new_inner(spis, irq, cs.map_into(), sck.map_into(), Some(miso.map_into()), None, config)
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}
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fn new_inner(
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spis: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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cs: PeripheralRef<'d, AnyPin>,
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sck: PeripheralRef<'d, AnyPin>,
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miso: Option<PeripheralRef<'d, AnyPin>>,
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mosi: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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) -> Self {
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into_ref!(cs, spis, irq);
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let r = T::regs();
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// Configure pins
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sck.conf().write(|w| w.input().connect().drive().h0h1());
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cs.conf().write(|w| w.input().connect().drive().h0h1());
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if let Some(mosi) = &mosi {
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mosi.conf().write(|w| w.input().connect().drive().h0h1());
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}
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if let Some(miso) = &miso {
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miso.conf().write(|w| w.dir().output().drive().h0h1());
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}
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match config.mode.polarity {
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Polarity::IdleHigh => {
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sck.set_high();
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if let Some(mosi) = &mosi {
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mosi.set_high();
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}
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}
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Polarity::IdleLow => {
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sck.set_low();
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if let Some(mosi) = &mosi {
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mosi.set_low();
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}
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}
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}
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if config.auto_acquire {
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r.shorts.write(|w| w.end_acquire().bit(true));
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}
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// Select pins.
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r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
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r.psel.csn.write(|w| unsafe { w.bits(cs.psel_bits()) });
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r.psel.mosi.write(|w| unsafe { w.bits(mosi.psel_bits()) });
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r.psel.miso.write(|w| unsafe { w.bits(miso.psel_bits()) });
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// Enable SPIS instance.
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r.enable.write(|w| w.enable().enabled());
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// Configure mode.
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let mode = config.mode;
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r.config.write(|w| {
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match mode {
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MODE_0 => {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().leading();
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}
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MODE_1 => {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().trailing();
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}
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MODE_2 => {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().leading();
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}
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MODE_3 => {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().trailing();
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}
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}
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w
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});
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// Set over-read character
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let orc = config.orc;
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r.orc.write(|w| unsafe { w.orc().bits(orc) });
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// Set default character
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let def = config.def;
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r.def.write(|w| unsafe { w.def().bits(def) });
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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Self { _p: spis }
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}
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fn on_interrupt(_: *mut ()) {
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let r = T::regs();
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let s = T::state();
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if r.events_end.read().bits() != 0 {
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s.end_waker.wake();
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r.intenclr.write(|w| w.end().clear());
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}
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if r.events_acquired.read().bits() != 0 {
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s.acquire_waker.wake();
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r.intenclr.write(|w| w.acquired().clear());
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}
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}
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fn prepare(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(), Error> {
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slice_in_ram_or(tx, Error::DMABufferNotInDataMemory)?;
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// NOTE: RAM slice check for rx is not necessary, as a mutable
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// slice can only be built from data located in RAM.
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compiler_fence(Ordering::SeqCst);
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let r = T::regs();
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// Set up the DMA write.
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let (ptr, len) = slice_ptr_parts(tx);
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
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r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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// Set up the DMA read.
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let (ptr, len) = slice_ptr_parts_mut(rx);
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r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as _) });
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r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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// Reset and enable the end event
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r.events_end.reset();
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r.intenset.write(|w| w.end().set());
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// Release the semaphore
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r.tasks_release.write(|w| unsafe { w.bits(1) });
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Ok(())
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}
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fn blocking_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(usize, usize), Error> {
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self.prepare(rx, tx)?;
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let r = T::regs();
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// Wait for 'end' event.
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while r.events_end.read().bits() == 0 {}
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let n_rx = r.rxd.amount.read().bits() as usize;
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let n_tx = r.txd.amount.read().bits() as usize;
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compiler_fence(Ordering::SeqCst);
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Ok((n_rx, n_tx))
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}
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fn blocking_inner(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(usize, usize), Error> {
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match self.blocking_inner_from_ram(rx, tx) {
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Ok(n) => Ok(n),
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Err(Error::DMABufferNotInDataMemory) => {
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trace!("Copying SPIS tx buffer into RAM for DMA");
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let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
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tx_ram_buf.copy_from_slice(tx);
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self.blocking_inner_from_ram(rx, tx_ram_buf)
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}
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Err(error) => Err(error),
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}
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}
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async fn async_inner_from_ram(&mut self, rx: *mut [u8], tx: *const [u8]) -> Result<(usize, usize), Error> {
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let r = T::regs();
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let s = T::state();
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if r.semstat.read().bits() != 1 {
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// Reset and enable the acquire event
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r.events_acquired.reset();
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r.intenset.write(|w| w.acquired().set());
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// Requests acquiring the SPIS semaphore
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r.tasks_acquire.write(|w| unsafe { w.bits(1) });
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// Wait for 'acquire' event.
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poll_fn(|cx| {
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s.acquire_waker.register(cx.waker());
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if r.events_acquired.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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}
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self.prepare(rx, tx)?;
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// Wait for 'end' event.
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poll_fn(|cx| {
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s.end_waker.register(cx.waker());
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if r.events_end.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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let n_rx = r.rxd.amount.read().bits() as usize;
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let n_tx = r.txd.amount.read().bits() as usize;
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compiler_fence(Ordering::SeqCst);
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Ok((n_rx, n_tx))
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}
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async fn async_inner(&mut self, rx: &mut [u8], tx: &[u8]) -> Result<(usize, usize), Error> {
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match self.async_inner_from_ram(rx, tx).await {
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Ok(n) => Ok(n),
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Err(Error::DMABufferNotInDataMemory) => {
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trace!("Copying SPIS tx buffer into RAM for DMA");
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let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
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tx_ram_buf.copy_from_slice(tx);
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self.async_inner_from_ram(rx, tx_ram_buf).await
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}
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Err(error) => Err(error),
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}
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}
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/// Reads data from the SPI bus without sending anything. Blocks until the buffer has been filled.
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/// Returns number of bytes read
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pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
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self.blocking_inner(data, &[]).map(|n| n.0)
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}
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/// Simultaneously sends and receives data. Blocks until the transmission is completed.
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/// If necessary, the write buffer will be copied into RAM (see struct description for detail).
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/// Returns number of bytes transferred `(n_rx, n_tx)`
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pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
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self.blocking_inner(read, write)
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}
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/// Same as [`blocking_transfer`](Spis::blocking_transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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/// Returns number of bytes transferred `(n_rx, n_tx)`
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pub fn blocking_transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
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self.blocking_inner(read, write)
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}
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/// Simultaneously sends and receives data.
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/// Places the received data into the same buffer and blocks until the transmission is completed.
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/// Returns number of bytes transferred
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pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<usize, Error> {
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self.blocking_inner_from_ram(data, data).map(|n| n.0)
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}
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/// Sends data, discarding any received data. Blocks until the transmission is completed.
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/// If necessary, the write buffer will be copied into RAM (see struct description for detail).
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/// Returns number of bytes written
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|
|
pub fn blocking_write(&mut self, data: &[u8]) -> Result<usize, Error> {
|
||
|
|
self.blocking_inner(&mut [], data).map(|n| n.1)
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Same as [`blocking_write`](Spis::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
|
||
|
|
/// Returns number of bytes written
|
||
|
|
pub fn blocking_write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
|
||
|
|
self.blocking_inner(&mut [], data).map(|n| n.1)
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Reads data from the SPI bus without sending anything.
|
||
|
|
/// Returns number of bytes read
|
||
|
|
pub async fn read(&mut self, data: &mut [u8]) -> Result<usize, Error> {
|
||
|
|
self.async_inner(data, &[]).await.map(|n| n.0)
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Simultaneously sends and receives data.
|
||
|
|
/// If necessary, the write buffer will be copied into RAM (see struct description for detail).
|
||
|
|
/// Returns number of bytes transferred `(n_rx, n_tx)`
|
||
|
|
pub async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
|
||
|
|
self.async_inner(read, write).await
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Same as [`transfer`](Spis::transfer) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
|
||
|
|
/// Returns number of bytes transferred `(n_rx, n_tx)`
|
||
|
|
pub async fn transfer_from_ram(&mut self, read: &mut [u8], write: &[u8]) -> Result<(usize, usize), Error> {
|
||
|
|
self.async_inner_from_ram(read, write).await
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Simultaneously sends and receives data. Places the received data into the same buffer.
|
||
|
|
/// Returns number of bytes transferred
|
||
|
|
pub async fn transfer_in_place(&mut self, data: &mut [u8]) -> Result<usize, Error> {
|
||
|
|
self.async_inner_from_ram(data, data).await.map(|n| n.0)
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Sends data, discarding any received data.
|
||
|
|
/// If necessary, the write buffer will be copied into RAM (see struct description for detail).
|
||
|
|
/// Returns number of bytes written
|
||
|
|
pub async fn write(&mut self, data: &[u8]) -> Result<usize, Error> {
|
||
|
|
self.async_inner(&mut [], data).await.map(|n| n.1)
|
||
|
|
}
|
||
|
|
|
||
|
|
/// Same as [`write`](Spis::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
|
||
|
|
/// Returns number of bytes written
|
||
|
|
pub async fn write_from_ram(&mut self, data: &[u8]) -> Result<usize, Error> {
|
||
|
|
self.async_inner_from_ram(&mut [], data).await.map(|n| n.1)
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
impl<'d, T: Instance> Drop for Spis<'d, T> {
|
||
|
|
fn drop(&mut self) {
|
||
|
|
trace!("spis drop");
|
||
|
|
|
||
|
|
// Disable
|
||
|
|
let r = T::regs();
|
||
|
|
r.enable.write(|w| w.enable().disabled());
|
||
|
|
|
||
|
|
gpio::deconfigure_pin(r.psel.sck.read().bits());
|
||
|
|
gpio::deconfigure_pin(r.psel.csn.read().bits());
|
||
|
|
gpio::deconfigure_pin(r.psel.miso.read().bits());
|
||
|
|
gpio::deconfigure_pin(r.psel.mosi.read().bits());
|
||
|
|
|
||
|
|
trace!("spis drop: done");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
pub(crate) mod sealed {
|
||
|
|
use embassy_sync::waitqueue::AtomicWaker;
|
||
|
|
|
||
|
|
use super::*;
|
||
|
|
|
||
|
|
pub struct State {
|
||
|
|
pub end_waker: AtomicWaker,
|
||
|
|
pub acquire_waker: AtomicWaker,
|
||
|
|
}
|
||
|
|
|
||
|
|
impl State {
|
||
|
|
pub const fn new() -> Self {
|
||
|
|
Self {
|
||
|
|
end_waker: AtomicWaker::new(),
|
||
|
|
acquire_waker: AtomicWaker::new(),
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
pub trait Instance {
|
||
|
|
fn regs() -> &'static pac::spis0::RegisterBlock;
|
||
|
|
fn state() -> &'static State;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
|
||
|
|
type Interrupt: Interrupt;
|
||
|
|
}
|
||
|
|
|
||
|
|
macro_rules! impl_spis {
|
||
|
|
($type:ident, $pac_type:ident, $irq:ident) => {
|
||
|
|
impl crate::spis::sealed::Instance for peripherals::$type {
|
||
|
|
fn regs() -> &'static pac::spis0::RegisterBlock {
|
||
|
|
unsafe { &*pac::$pac_type::ptr() }
|
||
|
|
}
|
||
|
|
fn state() -> &'static crate::spis::sealed::State {
|
||
|
|
static STATE: crate::spis::sealed::State = crate::spis::sealed::State::new();
|
||
|
|
&STATE
|
||
|
|
}
|
||
|
|
}
|
||
|
|
impl crate::spis::Instance for peripherals::$type {
|
||
|
|
type Interrupt = crate::interrupt::$irq;
|
||
|
|
}
|
||
|
|
};
|
||
|
|
}
|
||
|
|
|
||
|
|
// ====================
|
||
|
|
|
||
|
|
impl<'d, T: Instance> SetConfig for Spis<'d, T> {
|
||
|
|
type Config = Config;
|
||
|
|
fn set_config(&mut self, config: &Self::Config) {
|
||
|
|
let r = T::regs();
|
||
|
|
// Configure mode.
|
||
|
|
let mode = config.mode;
|
||
|
|
r.config.write(|w| {
|
||
|
|
match mode {
|
||
|
|
MODE_0 => {
|
||
|
|
w.order().msb_first();
|
||
|
|
w.cpol().active_high();
|
||
|
|
w.cpha().leading();
|
||
|
|
}
|
||
|
|
MODE_1 => {
|
||
|
|
w.order().msb_first();
|
||
|
|
w.cpol().active_high();
|
||
|
|
w.cpha().trailing();
|
||
|
|
}
|
||
|
|
MODE_2 => {
|
||
|
|
w.order().msb_first();
|
||
|
|
w.cpol().active_low();
|
||
|
|
w.cpha().leading();
|
||
|
|
}
|
||
|
|
MODE_3 => {
|
||
|
|
w.order().msb_first();
|
||
|
|
w.cpol().active_low();
|
||
|
|
w.cpha().trailing();
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
w
|
||
|
|
});
|
||
|
|
|
||
|
|
// Set over-read character
|
||
|
|
let orc = config.orc;
|
||
|
|
r.orc.write(|w| unsafe { w.orc().bits(orc) });
|
||
|
|
|
||
|
|
// Set default character
|
||
|
|
let def = config.def;
|
||
|
|
r.def.write(|w| unsafe { w.def().bits(def) });
|
||
|
|
|
||
|
|
// Set auto acquire
|
||
|
|
let auto_acquire = config.auto_acquire;
|
||
|
|
r.shorts.write(|w| w.end_acquire().bit(auto_acquire));
|
||
|
|
|
||
|
|
}
|
||
|
|
}
|