2021-05-11 03:04:59 +02:00
|
|
|
#![macro_use]
|
|
|
|
|
2021-06-26 09:58:36 +02:00
|
|
|
use core::marker::PhantomData;
|
|
|
|
use core::task::Poll;
|
|
|
|
|
2021-09-11 01:53:53 +02:00
|
|
|
use embassy::waitqueue::AtomicWaker;
|
|
|
|
use embassy_hal_common::drop::OnDrop;
|
2022-07-23 14:00:19 +02:00
|
|
|
use embassy_hal_common::into_ref;
|
2021-06-26 09:58:36 +02:00
|
|
|
use futures::future::poll_fn;
|
2021-03-28 22:40:41 +02:00
|
|
|
|
2022-06-12 22:15:44 +02:00
|
|
|
use crate::interrupt::{Interrupt, InterruptExt};
|
2021-10-19 10:13:08 +02:00
|
|
|
use crate::ppi::{Event, Task};
|
2022-07-23 14:00:19 +02:00
|
|
|
use crate::{pac, Peripheral};
|
2021-03-28 22:40:41 +02:00
|
|
|
|
2021-05-11 03:04:59 +02:00
|
|
|
pub(crate) mod sealed {
|
2021-06-26 09:58:36 +02:00
|
|
|
|
2021-03-28 22:40:41 +02:00
|
|
|
use super::*;
|
|
|
|
|
|
|
|
pub trait Instance {
|
2021-06-26 09:58:36 +02:00
|
|
|
/// The number of CC registers this instance has.
|
|
|
|
const CCS: usize;
|
|
|
|
fn regs() -> &'static pac::timer0::RegisterBlock;
|
|
|
|
/// Storage for the waker for CC register `n`.
|
|
|
|
fn waker(n: usize) -> &'static AtomicWaker;
|
2021-03-28 22:40:41 +02:00
|
|
|
}
|
|
|
|
pub trait ExtendedInstance {}
|
2021-09-01 16:16:56 +02:00
|
|
|
|
|
|
|
pub trait TimerType {}
|
2021-03-28 22:40:41 +02:00
|
|
|
}
|
|
|
|
|
2022-07-23 14:00:19 +02:00
|
|
|
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
|
2021-03-28 22:40:41 +02:00
|
|
|
type Interrupt: Interrupt;
|
|
|
|
}
|
|
|
|
pub trait ExtendedInstance: Instance + sealed::ExtendedInstance {}
|
|
|
|
|
2021-05-11 03:04:59 +02:00
|
|
|
macro_rules! impl_timer {
|
2021-06-26 09:58:36 +02:00
|
|
|
($type:ident, $pac_type:ident, $irq:ident, $ccs:literal) => {
|
2021-05-11 03:04:59 +02:00
|
|
|
impl crate::timer::sealed::Instance for peripherals::$type {
|
2021-06-26 09:58:36 +02:00
|
|
|
const CCS: usize = $ccs;
|
|
|
|
fn regs() -> &'static pac::timer0::RegisterBlock {
|
2021-05-11 03:04:59 +02:00
|
|
|
unsafe { &*(pac::$pac_type::ptr() as *const pac::timer0::RegisterBlock) }
|
2021-03-28 22:40:41 +02:00
|
|
|
}
|
2021-09-11 01:53:53 +02:00
|
|
|
fn waker(n: usize) -> &'static ::embassy::waitqueue::AtomicWaker {
|
|
|
|
use ::embassy::waitqueue::AtomicWaker;
|
2021-06-26 09:58:36 +02:00
|
|
|
const NEW_AW: AtomicWaker = AtomicWaker::new();
|
|
|
|
static WAKERS: [AtomicWaker; $ccs] = [NEW_AW; $ccs];
|
|
|
|
&WAKERS[n]
|
|
|
|
}
|
2021-03-28 22:40:41 +02:00
|
|
|
}
|
2021-05-11 03:04:59 +02:00
|
|
|
impl crate::timer::Instance for peripherals::$type {
|
|
|
|
type Interrupt = crate::interrupt::$irq;
|
2021-03-28 22:40:41 +02:00
|
|
|
}
|
|
|
|
};
|
2021-06-26 09:58:36 +02:00
|
|
|
($type:ident, $pac_type:ident, $irq:ident) => {
|
|
|
|
impl_timer!($type, $pac_type, $irq, 4);
|
|
|
|
};
|
2021-05-11 03:04:59 +02:00
|
|
|
($type:ident, $pac_type:ident, $irq:ident, extended) => {
|
2021-06-26 09:58:36 +02:00
|
|
|
impl_timer!($type, $pac_type, $irq, 6);
|
2021-05-11 03:04:59 +02:00
|
|
|
impl crate::timer::sealed::ExtendedInstance for peripherals::$type {}
|
|
|
|
impl crate::timer::ExtendedInstance for peripherals::$type {}
|
2021-03-28 22:40:41 +02:00
|
|
|
};
|
|
|
|
}
|
2021-06-26 09:58:36 +02:00
|
|
|
|
|
|
|
#[repr(u8)]
|
|
|
|
pub enum Frequency {
|
2021-06-29 03:29:32 +02:00
|
|
|
// I'd prefer not to prefix these with `F`, but Rust identifiers can't start with digits.
|
2021-06-26 09:58:36 +02:00
|
|
|
F16MHz = 0,
|
|
|
|
F8MHz = 1,
|
|
|
|
F4MHz = 2,
|
|
|
|
F2MHz = 3,
|
|
|
|
F1MHz = 4,
|
|
|
|
F500kHz = 5,
|
|
|
|
F250kHz = 6,
|
|
|
|
F125kHz = 7,
|
|
|
|
F62500Hz = 8,
|
|
|
|
F31250Hz = 9,
|
|
|
|
}
|
|
|
|
|
|
|
|
/// nRF Timer driver.
|
|
|
|
///
|
|
|
|
/// The timer has an internal counter, which is incremented for every tick of the timer.
|
|
|
|
/// The counter is 32-bit, so it wraps back to 0 at 4294967296.
|
|
|
|
///
|
|
|
|
/// It has either 4 or 6 Capture/Compare registers, which can be used to capture the current state of the counter
|
|
|
|
/// or trigger an event when the counter reaches a certain value.
|
2021-09-01 16:16:56 +02:00
|
|
|
|
|
|
|
pub trait TimerType: sealed::TimerType {}
|
|
|
|
|
|
|
|
pub enum Awaitable {}
|
|
|
|
pub enum NotAwaitable {}
|
|
|
|
|
|
|
|
impl sealed::TimerType for Awaitable {}
|
|
|
|
impl sealed::TimerType for NotAwaitable {}
|
|
|
|
impl TimerType for Awaitable {}
|
|
|
|
impl TimerType for NotAwaitable {}
|
|
|
|
|
2021-09-02 12:02:31 +02:00
|
|
|
pub struct Timer<'d, T: Instance, I: TimerType = NotAwaitable> {
|
2021-09-01 16:16:56 +02:00
|
|
|
phantom: PhantomData<(&'d mut T, I)>,
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
2021-09-01 16:16:56 +02:00
|
|
|
impl<'d, T: Instance> Timer<'d, T, Awaitable> {
|
2022-07-23 14:00:19 +02:00
|
|
|
pub fn new_awaitable(timer: impl Peripheral<P = T> + 'd, irq: impl Peripheral<P = T::Interrupt> + 'd) -> Self {
|
|
|
|
into_ref!(irq);
|
2021-06-26 09:58:36 +02:00
|
|
|
|
|
|
|
irq.set_handler(Self::on_interrupt);
|
|
|
|
irq.unpend();
|
|
|
|
irq.enable();
|
|
|
|
|
|
|
|
Self::new_irqless(timer)
|
|
|
|
}
|
2021-09-01 16:16:56 +02:00
|
|
|
}
|
|
|
|
impl<'d, T: Instance> Timer<'d, T, NotAwaitable> {
|
2021-09-02 12:02:31 +02:00
|
|
|
/// Create a `Timer` without an interrupt, meaning `Cc::wait` won't work.
|
|
|
|
///
|
|
|
|
/// This can be useful for triggering tasks via PPI
|
|
|
|
/// `Uarte` uses this internally.
|
2022-07-23 14:00:19 +02:00
|
|
|
pub fn new(timer: impl Peripheral<P = T> + 'd) -> Self {
|
2021-09-01 16:16:56 +02:00
|
|
|
Self::new_irqless(timer)
|
|
|
|
}
|
|
|
|
}
|
2021-06-26 09:58:36 +02:00
|
|
|
|
2021-09-01 16:16:56 +02:00
|
|
|
impl<'d, T: Instance, I: TimerType> Timer<'d, T, I> {
|
2021-06-26 09:58:36 +02:00
|
|
|
/// Create a `Timer` without an interrupt, meaning `Cc::wait` won't work.
|
|
|
|
///
|
2021-09-02 12:02:31 +02:00
|
|
|
/// This is used by the public constructors.
|
2022-07-23 14:00:19 +02:00
|
|
|
fn new_irqless(_timer: impl Peripheral<P = T> + 'd) -> Self {
|
2021-06-26 09:58:36 +02:00
|
|
|
let regs = T::regs();
|
|
|
|
|
2022-06-12 22:15:44 +02:00
|
|
|
let mut this = Self { phantom: PhantomData };
|
2021-06-29 03:29:32 +02:00
|
|
|
|
|
|
|
// Stop the timer before doing anything else,
|
|
|
|
// since changing BITMODE while running can cause 'unpredictable behaviour' according to the specification.
|
|
|
|
this.stop();
|
|
|
|
|
2021-06-26 09:58:36 +02:00
|
|
|
// Set the instance to timer mode.
|
|
|
|
regs.mode.write(|w| w.mode().timer());
|
|
|
|
|
|
|
|
// Make the counter's max value as high as possible.
|
|
|
|
// TODO: is there a reason someone would want to set this lower?
|
|
|
|
regs.bitmode.write(|w| w.bitmode()._32bit());
|
|
|
|
|
|
|
|
// Initialize the counter at 0.
|
|
|
|
this.clear();
|
|
|
|
|
2021-06-29 03:29:32 +02:00
|
|
|
// Default to the max frequency of the lower power clock
|
|
|
|
this.set_frequency(Frequency::F1MHz);
|
|
|
|
|
2021-06-26 09:58:36 +02:00
|
|
|
for n in 0..T::CCS {
|
2021-06-29 02:33:41 +02:00
|
|
|
let cc = this.cc(n);
|
|
|
|
// Initialize all the shorts as disabled.
|
2021-06-26 09:58:36 +02:00
|
|
|
cc.unshort_compare_clear();
|
|
|
|
cc.unshort_compare_stop();
|
2021-06-29 02:33:41 +02:00
|
|
|
// Initialize the CC registers as 0.
|
|
|
|
cc.write(0);
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
this
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Starts the timer.
|
|
|
|
pub fn start(&self) {
|
2021-06-29 05:04:05 +02:00
|
|
|
T::regs().tasks_start.write(|w| unsafe { w.bits(1) })
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Stops the timer.
|
|
|
|
pub fn stop(&self) {
|
2021-06-29 05:04:05 +02:00
|
|
|
T::regs().tasks_stop.write(|w| unsafe { w.bits(1) })
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Reset the timer's counter to 0.
|
|
|
|
pub fn clear(&self) {
|
2021-06-29 05:04:05 +02:00
|
|
|
T::regs().tasks_clear.write(|w| unsafe { w.bits(1) })
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns the START task, for use with PPI.
|
|
|
|
///
|
|
|
|
/// When triggered, this task starts the timer.
|
|
|
|
pub fn task_start(&self) -> Task {
|
2021-10-18 16:23:39 +02:00
|
|
|
Task::from_reg(&T::regs().tasks_start)
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns the STOP task, for use with PPI.
|
|
|
|
///
|
|
|
|
/// When triggered, this task stops the timer.
|
|
|
|
pub fn task_stop(&self) -> Task {
|
2021-10-18 16:23:39 +02:00
|
|
|
Task::from_reg(&T::regs().tasks_stop)
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns the CLEAR task, for use with PPI.
|
|
|
|
///
|
|
|
|
/// When triggered, this task resets the timer's counter to 0.
|
|
|
|
pub fn task_clear(&self) -> Task {
|
2021-10-18 16:23:39 +02:00
|
|
|
Task::from_reg(&T::regs().tasks_clear)
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Change the timer's frequency.
|
|
|
|
///
|
|
|
|
/// This will stop the timer if it isn't already stopped,
|
|
|
|
/// because the timer may exhibit 'unpredictable behaviour' if it's frequency is changed while it's running.
|
|
|
|
pub fn set_frequency(&self, frequency: Frequency) {
|
|
|
|
self.stop();
|
|
|
|
|
|
|
|
T::regs()
|
|
|
|
.prescaler
|
|
|
|
// SAFETY: `frequency` is a variant of `Frequency`,
|
|
|
|
// whose values are all in the range of 0-9 (the valid range of `prescaler`).
|
|
|
|
.write(|w| unsafe { w.prescaler().bits(frequency as u8) })
|
|
|
|
}
|
|
|
|
|
|
|
|
fn on_interrupt(_: *mut ()) {
|
|
|
|
let regs = T::regs();
|
|
|
|
for n in 0..T::CCS {
|
2021-06-29 05:04:05 +02:00
|
|
|
if regs.events_compare[n].read().bits() != 0 {
|
2021-06-29 02:33:41 +02:00
|
|
|
// Clear the interrupt, otherwise the interrupt will be repeatedly raised as soon as the interrupt handler exits.
|
|
|
|
// We can't clear the event, because it's used to poll whether the future is done or still pending.
|
2021-06-29 06:37:37 +02:00
|
|
|
regs.intenclr
|
|
|
|
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << (16 + n))) });
|
2021-06-26 09:58:36 +02:00
|
|
|
T::waker(n).wake();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-06-29 02:33:41 +02:00
|
|
|
/// Returns this timer's `n`th CC register.
|
|
|
|
///
|
|
|
|
/// # Panics
|
|
|
|
/// Panics if `n` >= the number of CC registers this timer has (4 for a normal timer, 6 for an extended timer).
|
2021-09-01 16:16:56 +02:00
|
|
|
pub fn cc(&mut self, n: usize) -> Cc<T, I> {
|
2021-06-29 02:33:41 +02:00
|
|
|
if n >= T::CCS {
|
2022-06-12 22:15:44 +02:00
|
|
|
panic!("Cannot get CC register {} of timer with {} CC registers.", n, T::CCS);
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
Cc {
|
2021-06-29 02:33:41 +02:00
|
|
|
n,
|
2021-06-26 09:58:36 +02:00
|
|
|
phantom: PhantomData,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// A representation of a timer's Capture/Compare (CC) register.
|
|
|
|
///
|
|
|
|
/// A CC register holds a 32-bit value.
|
|
|
|
/// This is used either to store a capture of the timer's current count, or to specify the value for the timer to compare against.
|
|
|
|
///
|
|
|
|
/// The timer will fire the register's COMPARE event when its counter reaches the value stored in the register.
|
|
|
|
/// When the register's CAPTURE task is triggered, the timer will store the current value of its counter in the register
|
2021-09-02 12:02:31 +02:00
|
|
|
pub struct Cc<'a, T: Instance, I: TimerType = NotAwaitable> {
|
2021-06-26 09:58:36 +02:00
|
|
|
n: usize,
|
2021-09-02 12:02:31 +02:00
|
|
|
phantom: PhantomData<(&'a mut T, I)>,
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
2021-09-01 16:20:32 +02:00
|
|
|
impl<'a, T: Instance> Cc<'a, T, Awaitable> {
|
|
|
|
/// Wait until the timer's counter reaches the value stored in this register.
|
|
|
|
///
|
|
|
|
/// This requires a mutable reference so that this task's waker cannot be overwritten by a second call to `wait`.
|
|
|
|
pub async fn wait(&mut self) {
|
|
|
|
let regs = T::regs();
|
|
|
|
|
|
|
|
// Enable the interrupt for this CC's COMPARE event.
|
|
|
|
regs.intenset
|
|
|
|
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << (16 + self.n))) });
|
|
|
|
|
|
|
|
// Disable the interrupt if the future is dropped.
|
|
|
|
let on_drop = OnDrop::new(|| {
|
|
|
|
regs.intenclr
|
|
|
|
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << (16 + self.n))) });
|
|
|
|
});
|
|
|
|
|
|
|
|
poll_fn(|cx| {
|
|
|
|
T::waker(self.n).register(cx.waker());
|
|
|
|
|
|
|
|
if regs.events_compare[self.n].read().bits() != 0 {
|
|
|
|
// Reset the register for next time
|
|
|
|
regs.events_compare[self.n].reset();
|
|
|
|
Poll::Ready(())
|
|
|
|
} else {
|
|
|
|
Poll::Pending
|
|
|
|
}
|
|
|
|
})
|
|
|
|
.await;
|
|
|
|
|
|
|
|
// The interrupt was already disabled in the interrupt handler, so there's no need to disable it again.
|
|
|
|
on_drop.defuse();
|
|
|
|
}
|
|
|
|
}
|
2021-09-01 16:16:56 +02:00
|
|
|
impl<'a, T: Instance> Cc<'a, T, NotAwaitable> {}
|
|
|
|
|
|
|
|
impl<'a, T: Instance, I: TimerType> Cc<'a, T, I> {
|
2021-06-26 09:58:36 +02:00
|
|
|
/// Get the current value stored in the register.
|
2021-06-29 02:33:41 +02:00
|
|
|
pub fn read(&self) -> u32 {
|
2021-06-26 09:58:36 +02:00
|
|
|
T::regs().cc[self.n].read().cc().bits()
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Set the value stored in the register.
|
|
|
|
///
|
|
|
|
/// `event_compare` will fire when the timer's counter reaches this value.
|
2021-06-29 02:33:41 +02:00
|
|
|
pub fn write(&self, value: u32) {
|
2021-06-26 09:58:36 +02:00
|
|
|
// SAFETY: there are no invalid values for the CC register.
|
|
|
|
T::regs().cc[self.n].write(|w| unsafe { w.cc().bits(value) })
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Capture the current value of the timer's counter in this register, and return it.
|
|
|
|
pub fn capture(&self) -> u32 {
|
2021-06-29 05:04:05 +02:00
|
|
|
T::regs().tasks_capture[self.n].write(|w| unsafe { w.bits(1) });
|
2021-06-29 02:33:41 +02:00
|
|
|
self.read()
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns this CC register's CAPTURE task, for use with PPI.
|
|
|
|
///
|
|
|
|
/// When triggered, this task will capture the current value of the timer's counter in this register.
|
|
|
|
pub fn task_capture(&self) -> Task {
|
2021-10-18 16:23:39 +02:00
|
|
|
Task::from_reg(&T::regs().tasks_capture)
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Returns this CC register's COMPARE event, for use with PPI.
|
|
|
|
///
|
|
|
|
/// This event will fire when the timer's counter reaches the value in this CC register.
|
|
|
|
pub fn event_compare(&self) -> Event {
|
2021-10-18 16:23:39 +02:00
|
|
|
Event::from_reg(&T::regs().events_compare[self.n])
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Enable the shortcut between this CC register's COMPARE event and the timer's CLEAR task.
|
|
|
|
///
|
|
|
|
/// This means that when the COMPARE event is fired, the CLEAR task will be triggered.
|
|
|
|
///
|
|
|
|
/// So, when the timer's counter reaches the value stored in this register, the timer's counter will be reset to 0.
|
|
|
|
pub fn short_compare_clear(&self) {
|
2021-06-29 06:37:37 +02:00
|
|
|
T::regs()
|
|
|
|
.shorts
|
|
|
|
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << self.n)) })
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Disable the shortcut between this CC register's COMPARE event and the timer's CLEAR task.
|
|
|
|
pub fn unshort_compare_clear(&self) {
|
2021-06-29 06:37:37 +02:00
|
|
|
T::regs()
|
|
|
|
.shorts
|
2021-06-29 07:12:42 +02:00
|
|
|
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << self.n)) })
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Enable the shortcut between this CC register's COMPARE event and the timer's STOP task.
|
|
|
|
///
|
|
|
|
/// This means that when the COMPARE event is fired, the STOP task will be triggered.
|
|
|
|
///
|
|
|
|
/// So, when the timer's counter reaches the value stored in this register, the timer will stop counting up.
|
|
|
|
pub fn short_compare_stop(&self) {
|
2021-06-29 06:37:37 +02:00
|
|
|
T::regs()
|
|
|
|
.shorts
|
|
|
|
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << (8 + self.n))) })
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
/// Disable the shortcut between this CC register's COMPARE event and the timer's STOP task.
|
|
|
|
pub fn unshort_compare_stop(&self) {
|
2021-06-29 06:37:37 +02:00
|
|
|
T::regs()
|
|
|
|
.shorts
|
2021-06-29 07:12:42 +02:00
|
|
|
.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << (8 + self.n))) })
|
2021-06-26 09:58:36 +02:00
|
|
|
}
|
|
|
|
}
|