2021-09-21 13:42:27 +02:00
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pub use super::types::*;
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use crate::pac;
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use crate::peripherals::{self, RCC};
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use crate::rcc::{get_freqs, set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::U32Ext;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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/// Most of clock setup is copied from rcc/l0
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/// HSI speed
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pub const HSI_FREQ: u32 = 16_000_000;
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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MSI(MSIRange),
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HSE(Hertz),
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HSI,
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}
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2021-09-23 14:43:17 +02:00
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type Ppre = u8;
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2021-09-21 13:42:27 +02:00
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impl Into<Ppre> for APBPrescaler {
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fn into(self) -> Ppre {
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match self {
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2021-09-23 14:43:17 +02:00
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APBPrescaler::NotDivided => 0b000,
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APBPrescaler::Div2 => 0b100,
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APBPrescaler::Div4 => 0b101,
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APBPrescaler::Div8 => 0b110,
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APBPrescaler::Div16 => 0b111,
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2021-09-21 13:42:27 +02:00
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}
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}
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}
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2021-09-23 14:43:17 +02:00
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type Hpre = u8;
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2021-09-21 13:42:27 +02:00
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impl Into<Hpre> for AHBPrescaler {
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fn into(self) -> Hpre {
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match self {
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2021-09-23 14:43:17 +02:00
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AHBPrescaler::NotDivided => 0b0000,
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AHBPrescaler::Div2 => 0b1000,
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AHBPrescaler::Div4 => 0b1001,
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AHBPrescaler::Div8 => 0b1010,
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AHBPrescaler::Div16 => 0b1011,
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AHBPrescaler::Div64 => 0b1100,
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AHBPrescaler::Div128 => 0b1101,
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AHBPrescaler::Div256 => 0b1110,
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AHBPrescaler::Div512 => 0b1111,
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2021-09-21 13:42:27 +02:00
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}
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}
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}
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impl Into<u8> for MSIRange {
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fn into(self) -> u8 {
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match self {
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MSIRange::Range0 => 0b000,
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MSIRange::Range1 => 0b001,
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MSIRange::Range2 => 0b010,
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MSIRange::Range3 => 0b011,
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MSIRange::Range4 => 0b100,
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MSIRange::Range5 => 0b101,
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MSIRange::Range6 => 0b110,
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}
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}
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}
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/// Clocks configutation
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pub struct Config {
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mux: ClockSrc,
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ahb_pre: AHBPrescaler,
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apb1_pre: APBPrescaler,
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apb2_pre: APBPrescaler,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::MSI(MSIRange::default()),
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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}
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}
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}
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impl Config {
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#[inline]
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pub fn clock_src(mut self, mux: ClockSrc) -> Self {
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self.mux = mux;
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self
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}
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#[inline]
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pub fn ahb_pre(mut self, pre: AHBPrescaler) -> Self {
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self.ahb_pre = pre;
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self
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}
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#[inline]
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pub fn apb1_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb1_pre = pre;
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self
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}
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#[inline]
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pub fn apb2_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb2_pre = pre;
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self
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}
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}
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/// RCC peripheral
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pub struct Rcc<'d> {
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_rb: peripherals::RCC,
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phantom: PhantomData<&'d mut peripherals::RCC>,
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}
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impl<'d> Rcc<'d> {
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pub fn new(rcc: impl Unborrow<Target = peripherals::RCC> + 'd) -> Self {
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unborrow!(rcc);
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Self {
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_rb: rcc,
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phantom: PhantomData,
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}
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}
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// Safety: RCC init must have been called
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pub fn clocks(&self) -> &'static Clocks {
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unsafe { get_freqs() }
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}
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}
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/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
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pub trait RccExt {
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fn freeze(self, config: Config) -> Clocks;
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}
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impl RccExt for RCC {
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// `cfgr` is almost always a constant, so make sure it can be constant-propagated properly by
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// marking this function and all `Config` constructors and setters as `#[inline]`.
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// This saves ~900 Bytes for the `pwr.rs` example.
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#[inline]
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fn freeze(self, cfgr: Config) -> Clocks {
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let rcc = pac::RCC;
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let (sys_clk, sw) = match cfgr.mux {
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ClockSrc::MSI(range) => {
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// Set MSI range
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unsafe {
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rcc.icscr().write(|w| w.set_msirange(range.into()));
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}
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// Enable MSI
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unsafe {
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rcc.cr().write(|w| w.set_msion(true));
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while !rcc.cr().read().msirdy() {}
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}
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let freq = 32_768 * (1 << (range as u8 + 1));
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2021-09-23 14:43:17 +02:00
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(freq, 0b00)
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2021-09-21 13:42:27 +02:00
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}
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ClockSrc::HSI => {
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// Enable HSI
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unsafe {
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rcc.cr().write(|w| w.set_hsion(true));
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while !rcc.cr().read().hsirdy() {}
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}
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2021-09-23 14:43:17 +02:00
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(HSI_FREQ, 0b01)
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2021-09-21 13:42:27 +02:00
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
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unsafe {
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rcc.cr().write(|w| w.set_hseon(true));
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while !rcc.cr().read().hserdy() {}
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}
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2021-09-23 14:43:17 +02:00
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(freq.0, 0b10)
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2021-09-21 13:42:27 +02:00
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}
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};
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unsafe {
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rcc.cfgr().modify(|w| {
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w.set_sw(sw.into());
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w.set_hpre(cfgr.ahb_pre.into());
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w.set_ppre1(cfgr.apb1_pre.into());
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w.set_ppre2(cfgr.apb2_pre.into());
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});
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}
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let ahb_freq: u32 = match cfgr.ahb_pre {
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AHBPrescaler::NotDivided => sys_clk,
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pre => {
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let pre: Hpre = pre.into();
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2021-09-23 14:43:17 +02:00
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let pre = 1 << (pre as u32 - 7);
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2021-09-21 13:42:27 +02:00
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sys_clk / pre
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}
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};
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let (apb1_freq, apb1_tim_freq) = match cfgr.apb1_pre {
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APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
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pre => {
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let pre: Ppre = pre.into();
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2021-09-23 14:43:17 +02:00
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let pre: u8 = 1 << (pre - 3);
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2021-09-21 13:42:27 +02:00
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match cfgr.apb2_pre {
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APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
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pre => {
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let pre: Ppre = pre.into();
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2021-09-23 14:43:17 +02:00
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let pre: u8 = 1 << (pre - 3);
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2021-09-21 13:42:27 +02:00
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let freq = ahb_freq / (1 << (pre as u8 - 3));
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(freq, freq * 2)
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}
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};
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Clocks {
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sys: sys_clk.hz(),
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ahb: ahb_freq.hz(),
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apb1: apb1_freq.hz(),
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apb2: apb2_freq.hz(),
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apb1_tim: apb1_tim_freq.hz(),
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apb2_tim: apb2_tim_freq.hz(),
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}
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}
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}
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pub unsafe fn init(config: Config) {
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let r = <peripherals::RCC as embassy::util::Steal>::steal();
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let clocks = r.freeze(config);
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set_freqs(clocks);
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}
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