2022-04-26 23:57:26 +02:00
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use core::sync::atomic::{fence, Ordering};
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use core::task::Waker;
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2022-08-22 21:46:09 +02:00
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use embassy_sync::waitqueue::AtomicWaker;
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2022-04-26 23:57:26 +02:00
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2022-06-12 22:15:44 +02:00
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use super::{Request, TransferOptions, Word, WordSize};
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2022-04-26 23:57:26 +02:00
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use crate::_generated::GPDMA_CHANNEL_COUNT;
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2022-06-12 22:15:44 +02:00
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use crate::interrupt::{Interrupt, InterruptExt};
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2022-04-26 23:57:26 +02:00
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use crate::pac::gpdma::{vals, Gpdma};
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2022-06-12 22:15:44 +02:00
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use crate::{interrupt, pac};
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2022-04-26 23:57:26 +02:00
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impl From<WordSize> for vals::ChTr1Dw {
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fn from(raw: WordSize) -> Self {
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match raw {
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WordSize::OneByte => Self::BYTE,
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WordSize::TwoBytes => Self::HALFWORD,
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WordSize::FourBytes => Self::WORD,
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}
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}
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}
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struct ChannelState {
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waker: AtomicWaker,
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}
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impl ChannelState {
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const fn new() -> Self {
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Self {
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waker: AtomicWaker::new(),
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}
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}
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}
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struct State {
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channels: [ChannelState; GPDMA_CHANNEL_COUNT],
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}
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impl State {
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const fn new() -> Self {
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const CH: ChannelState = ChannelState::new();
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Self {
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channels: [CH; GPDMA_CHANNEL_COUNT],
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}
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}
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}
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static STATE: State = State::new();
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/// safety: must be called only once
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pub(crate) unsafe fn init() {
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foreach_interrupt! {
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($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
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interrupt::$irq::steal().enable();
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};
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}
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crate::_generated::init_gpdma();
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}
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foreach_dma_channel! {
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($channel_peri:ident, $dma_peri:ident, gpdma, $channel_num:expr, $index:expr, $dmamux:tt) => {
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impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {
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unsafe fn start_write<W: Word>(&mut self, request: Request, buf: *const [W], reg_addr: *mut W, options: TransferOptions) {
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let (ptr, len) = super::slice_ptr_parts(buf);
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low_level_api::start_transfer(
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pac::$dma_peri,
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$channel_num,
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request,
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low_level_api::Dir::MemoryToPeripheral,
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reg_addr as *const u32,
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ptr as *mut u32,
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len,
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true,
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W::bits(),
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options,
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)
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}
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unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut W, options: TransferOptions) {
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let buf = [repeated];
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low_level_api::start_transfer(
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pac::$dma_peri,
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$channel_num,
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request,
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low_level_api::Dir::MemoryToPeripheral,
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reg_addr as *const u32,
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buf.as_ptr() as *mut u32,
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count,
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false,
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W::bits(),
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options,
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)
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}
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unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *const W, buf: *mut [W], options: TransferOptions) {
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let (ptr, len) = super::slice_ptr_parts_mut(buf);
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low_level_api::start_transfer(
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pac::$dma_peri,
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$channel_num,
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request,
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low_level_api::Dir::PeripheralToMemory,
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reg_addr as *const u32,
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ptr as *mut u32,
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len,
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true,
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W::bits(),
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options,
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);
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}
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unsafe fn start_double_buffered_read<W: Word>(
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&mut self,
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_request: Request,
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_reg_addr: *const W,
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_buffer0: *mut W,
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_buffer1: *mut W,
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_buffer_len: usize,
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_options: TransferOptions,
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) {
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panic!("Unsafe double buffered mode is unavailable on GPBDMA");
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}
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unsafe fn set_buffer0<W: Word>(&mut self, _buffer: *mut W) {
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panic!("Unsafe double buffered mode is unavailable on GPBDMA");
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}
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unsafe fn set_buffer1<W: Word>(&mut self, _buffer: *mut W) {
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panic!("Unsafe double buffered mode is unavailable on GPBDMA");
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}
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unsafe fn is_buffer0_accessible(&mut self) -> bool {
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panic!("Unsafe double buffered mode is unavailable on GPBDMA");
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}
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fn request_stop(&mut self) {
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unsafe {low_level_api::request_stop(pac::$dma_peri, $channel_num);}
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}
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fn is_running(&self) -> bool {
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unsafe {low_level_api::is_running(pac::$dma_peri, $channel_num)}
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}
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fn remaining_transfers(&mut self) -> u16 {
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unsafe {low_level_api::get_remaining_transfers(pac::$dma_peri, $channel_num)}
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}
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fn set_waker(&mut self, waker: &Waker) {
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unsafe {low_level_api::set_waker($index, waker )}
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}
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fn on_irq() {
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unsafe {
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low_level_api::on_irq_inner(pac::$dma_peri, $channel_num, $index);
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}
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}
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}
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impl crate::dma::Channel for crate::peripherals::$channel_peri { }
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};
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}
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mod low_level_api {
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use super::*;
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Dir {
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MemoryToPeripheral,
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PeripheralToMemory,
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}
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pub unsafe fn start_transfer(
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dma: Gpdma,
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channel_number: u8,
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request: Request,
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dir: Dir,
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peri_addr: *const u32,
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mem_addr: *mut u32,
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mem_len: usize,
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incr_mem: bool,
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data_size: WordSize,
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_options: TransferOptions,
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) {
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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let ch = dma.ch(channel_number as _);
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ch.llr().write(|_| {}); // no linked list
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ch.tr1().write(|w| {
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w.set_sdw(data_size.into());
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w.set_ddw(data_size.into());
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w.set_sinc(dir == Dir::MemoryToPeripheral && incr_mem);
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w.set_dinc(dir == Dir::PeripheralToMemory && incr_mem);
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});
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ch.tr2().write(|w| {
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w.set_dreq(match dir {
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Dir::MemoryToPeripheral => vals::ChTr2Dreq::DESTINATIONPERIPHERAL,
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Dir::PeripheralToMemory => vals::ChTr2Dreq::SOURCEPERIPHERAL,
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});
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w.set_reqsel(request);
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});
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ch.br1().write(|w| {
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// BNDT is specified as bytes, not as number of transfers.
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w.set_bndt((mem_len * data_size.bytes()) as u16)
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});
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match dir {
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Dir::MemoryToPeripheral => {
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ch.sar().write_value(mem_addr as _);
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ch.dar().write_value(peri_addr as _);
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}
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Dir::PeripheralToMemory => {
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ch.sar().write_value(peri_addr as _);
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ch.dar().write_value(mem_addr as _);
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}
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}
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ch.cr().write(|w| {
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// Enable interrupts
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w.set_tcie(true);
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w.set_useie(true);
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w.set_dteie(true);
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w.set_suspie(true);
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// Start it
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w.set_en(true);
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});
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}
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/// Stops the DMA channel.
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pub unsafe fn request_stop(dma: Gpdma, channel_number: u8) {
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// get a handle on the channel itself
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let ch = dma.ch(channel_number as _);
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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ch.cr().write(|w| {
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w.set_tcie(true);
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w.set_useie(true);
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w.set_dteie(true);
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w.set_suspie(true);
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});
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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}
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/// Gets the running status of the channel
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pub unsafe fn is_running(dma: Gpdma, ch: u8) -> bool {
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let ch = dma.ch(ch as _);
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!ch.sr().read().idlef()
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}
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/// Gets the total remaining transfers for the channel
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/// Note: this will be zero for transfers that completed without cancellation.
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pub unsafe fn get_remaining_transfers(dma: Gpdma, ch: u8) -> u16 {
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// get a handle on the channel itself
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let ch = dma.ch(ch as _);
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// read the remaining transfer count. If this is zero, the transfer completed fully.
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ch.br1().read().bndt()
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}
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/// Sets the waker for the specified DMA channel
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pub unsafe fn set_waker(state_number: usize, waker: &Waker) {
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STATE.channels[state_number].waker.register(waker);
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}
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/// Safety: Must be called with a matching set of parameters for a valid dma channel
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pub unsafe fn on_irq_inner(dma: Gpdma, channel_num: u8, state_index: u8) {
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let channel_num = channel_num as usize;
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let state_index = state_index as usize;
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let ch = dma.ch(channel_num);
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let sr = ch.sr().read();
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if sr.dtef() {
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panic!(
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"DMA: data transfer error on DMA@{:08x} channel {}",
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dma.0 as u32, channel_num
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);
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}
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if sr.usef() {
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panic!(
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"DMA: user settings error on DMA@{:08x} channel {}",
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dma.0 as u32, channel_num
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);
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}
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if sr.suspf() || sr.tcf() {
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ch.cr().write(|w| w.set_reset(true));
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STATE.channels[state_index].waker.wake();
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}
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}
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}
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