2023-05-31 04:14:25 +02:00
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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// required-features: can
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2023-06-19 23:11:01 +02:00
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#[path = "../common.rs"]
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mod common;
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use common::*;
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2023-05-31 04:14:25 +02:00
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use embassy_executor::Spawner;
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use embassy_stm32::bind_interrupts;
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use embassy_stm32::can::bxcan::filter::Mask32;
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use embassy_stm32::can::bxcan::{Fifo, Frame, StandardId};
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use embassy_stm32::can::{Can, Rx0InterruptHandler, Rx1InterruptHandler, SceInterruptHandler, TxInterruptHandler};
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use embassy_stm32::gpio::{Input, Pull};
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use embassy_stm32::peripherals::CAN1;
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use {defmt_rtt as _, panic_probe as _};
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bind_interrupts!(struct Irqs {
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CAN1_RX0 => Rx0InterruptHandler<CAN1>;
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CAN1_RX1 => Rx1InterruptHandler<CAN1>;
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CAN1_SCE => SceInterruptHandler<CAN1>;
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CAN1_TX => TxInterruptHandler<CAN1>;
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});
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let mut p = embassy_stm32::init(config());
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info!("Hello World!");
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// HW is connected as follows:
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// PB13 -> PD0
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// PB12 -> PD1
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// The next two lines are a workaround for testing without transceiver.
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// To synchronise to the bus the RX input needs to see a high level.
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// Use `mem::forget()` to release the borrow on the pin but keep the
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// pull-up resistor enabled.
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let rx_pin = Input::new(&mut p.PD0, Pull::Up);
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core::mem::forget(rx_pin);
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let mut can = Can::new(p.CAN1, p.PD0, p.PD1, Irqs);
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info!("Configuring can...");
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can.modify_filters().enable_bank(0, Fifo::Fifo0, Mask32::accept_all());
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can.set_bitrate(1_000_000);
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can.modify_config()
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.set_loopback(true) // Receive own frames
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.set_silent(true)
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// .set_bit_timing(0x001c0003)
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.enable();
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info!("Can configured");
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let mut i: u8 = 0;
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loop {
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let tx_frame = Frame::new_data(unwrap!(StandardId::new(i as _)), [i]);
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info!("Transmitting frame...");
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can.write(&tx_frame).await;
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info!("Receiving frame...");
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let (time, rx_frame) = can.read().await.unwrap();
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info!("loopback time {}", time);
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info!("loopback frame {=u8}", rx_frame.data().unwrap()[0]);
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i += 1;
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if i > 10 {
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break;
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}
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}
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info!("Test OK");
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cortex_m::asm::bkpt();
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}
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