2021-07-15 05:42:06 +02:00
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#![macro_use]
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2021-08-11 01:40:02 +02:00
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use core::sync::atomic::{fence, Ordering};
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2021-11-19 19:15:55 +01:00
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use core::task::Waker;
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2021-07-15 05:42:06 +02:00
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use embassy::interrupt::{Interrupt, InterruptExt};
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2021-09-11 01:53:53 +02:00
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use embassy::waitqueue::AtomicWaker;
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2021-07-15 05:42:06 +02:00
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2021-11-19 19:15:55 +01:00
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use crate::dma::Request;
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2021-07-15 05:42:06 +02:00
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use crate::pac;
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use crate::pac::bdma::vals;
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2021-11-19 19:15:55 +01:00
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use super::{Word, WordSize};
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impl From<WordSize> for vals::Size {
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fn from(raw: WordSize) -> Self {
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match raw {
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WordSize::OneByte => Self::BITS8,
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WordSize::TwoBytes => Self::BITS16,
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WordSize::FourBytes => Self::BITS32,
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}
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}
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}
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2021-07-15 05:42:06 +02:00
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const CH_COUNT: usize = pac::peripheral_count!(bdma) * 8;
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struct State {
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ch_wakers: [AtomicWaker; CH_COUNT],
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}
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impl State {
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const fn new() -> Self {
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const AW: AtomicWaker = AtomicWaker::new();
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Self {
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ch_wakers: [AW; CH_COUNT],
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}
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}
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}
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static STATE: State = State::new();
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macro_rules! dma_num {
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(DMA1) => {
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0
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};
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(DMA2) => {
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1
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};
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(BDMA) => {
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0
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};
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}
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2022-02-05 03:03:32 +01:00
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pub(crate) unsafe fn on_irq() {
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2021-07-15 05:42:06 +02:00
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pac::peripherals! {
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(bdma, $dma:ident) => {
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let isr = pac::$dma.isr().read();
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let dman = dma_num!($dma);
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2021-12-08 03:30:07 +01:00
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for chn in 0..pac::dma_channels_count!($dma) {
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2021-07-22 14:52:16 +02:00
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let cr = pac::$dma.ch(chn).cr();
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if isr.tcif(chn) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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let n = dma_num!($dma) * 8 + chn;
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2021-07-15 05:42:06 +02:00
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STATE.ch_wakers[n].wake();
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}
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}
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};
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}
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}
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/// safety: must be called only once
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pub(crate) unsafe fn init() {
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pac::interrupts! {
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2021-07-27 19:23:33 +02:00
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($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
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2021-07-15 05:42:06 +02:00
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crate::interrupt::$irq::steal().enable();
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};
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}
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2022-02-09 00:58:17 +01:00
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crate::generated::init_bdma();
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2021-07-15 05:42:06 +02:00
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}
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2021-07-17 07:35:59 +02:00
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pac::dma_channels! {
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($channel_peri:ident, $dma_peri:ident, bdma, $channel_num:expr, $dmamux:tt) => {
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2021-11-19 19:15:55 +01:00
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impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {
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2022-01-19 15:59:25 +01:00
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unsafe fn start_write<W: Word>(&mut self, request: Request, buf: *const[W], reg_addr: *mut W) {
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let (ptr, len) = super::slice_ptr_parts(buf);
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2021-11-19 19:15:55 +01:00
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low_level_api::start_transfer(
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2021-12-08 03:30:07 +01:00
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pac::$dma_peri,
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2021-11-19 19:15:55 +01:00
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$channel_num,
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#[cfg(any(bdma_v2, dmamux))]
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request,
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vals::Dir::FROMMEMORY,
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reg_addr as *const u32,
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2022-01-19 15:59:25 +01:00
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ptr as *mut u32,
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len,
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2021-11-19 19:15:55 +01:00
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true,
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vals::Size::from(W::bits()),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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);
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2021-07-15 05:42:06 +02:00
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}
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2021-11-19 19:15:55 +01:00
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2021-12-08 03:18:15 +01:00
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unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut W) {
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2021-11-19 19:15:55 +01:00
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let buf = [repeated];
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low_level_api::start_transfer(
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2021-12-08 03:30:07 +01:00
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pac::$dma_peri,
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2021-11-19 19:15:55 +01:00
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$channel_num,
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#[cfg(any(bdma_v2, dmamux))]
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request,
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vals::Dir::FROMMEMORY,
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reg_addr as *const u32,
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buf.as_ptr() as *mut u32,
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count,
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false,
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vals::Size::from(W::bits()),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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)
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2021-07-20 21:20:16 +02:00
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}
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2022-01-19 15:59:25 +01:00
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unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *const W, buf: *mut [W]) {
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let (ptr, len) = super::slice_ptr_parts_mut(buf);
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2021-11-19 19:15:55 +01:00
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low_level_api::start_transfer(
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2021-12-08 03:30:07 +01:00
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pac::$dma_peri,
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2021-11-19 19:15:55 +01:00
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$channel_num,
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#[cfg(any(bdma_v2, dmamux))]
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request,
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vals::Dir::FROMPERIPHERAL,
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reg_addr as *const u32,
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2022-01-19 15:59:25 +01:00
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ptr as *mut u32,
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len,
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2021-11-19 19:15:55 +01:00
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true,
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vals::Size::from(W::bits()),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_CH_NUM,
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);
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2021-07-15 05:42:06 +02:00
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}
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2021-11-19 19:15:55 +01:00
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fn request_stop(&mut self){
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2021-12-08 03:30:07 +01:00
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unsafe {low_level_api::request_stop(pac::$dma_peri, $channel_num);}
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2021-09-29 04:33:40 +02:00
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}
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2021-11-19 19:15:55 +01:00
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2021-12-08 01:51:39 +01:00
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fn is_running(&self) -> bool {
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2021-12-08 03:30:07 +01:00
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unsafe {low_level_api::is_running(pac::$dma_peri, $channel_num)}
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2021-09-29 04:33:40 +02:00
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}
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2021-11-19 19:15:55 +01:00
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fn remaining_transfers(&mut self) -> u16 {
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2021-12-08 03:30:07 +01:00
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unsafe {low_level_api::get_remaining_transfers(pac::$dma_peri, $channel_num)}
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2021-09-29 04:33:40 +02:00
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}
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2021-11-19 19:15:55 +01:00
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fn set_waker(&mut self, waker: &Waker) {
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2021-12-08 01:54:31 +01:00
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unsafe {low_level_api::set_waker(dma_num!($dma_peri) * 8 + $channel_num, waker )}
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2021-09-29 04:33:40 +02:00
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}
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2021-07-15 05:42:06 +02:00
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}
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2021-11-19 19:15:55 +01:00
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impl crate::dma::Channel for crate::peripherals::$channel_peri {}
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2021-07-15 05:42:06 +02:00
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};
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}
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2021-11-19 19:15:55 +01:00
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mod low_level_api {
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use super::*;
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pub unsafe fn start_transfer(
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dma: pac::bdma::Dma,
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channel_number: u8,
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#[cfg(any(bdma_v2, dmamux))] request: Request,
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dir: vals::Dir,
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peri_addr: *const u32,
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mem_addr: *mut u32,
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mem_len: usize,
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incr_mem: bool,
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data_size: vals::Size,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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) {
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let ch = dma.ch(channel_number as _);
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2021-12-08 03:30:07 +01:00
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reset_status(dma, channel_number);
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2021-11-19 19:15:55 +01:00
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#[cfg(dmamux)]
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super::super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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#[cfg(bdma_v2)]
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critical_section::with(|_| {
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dma.cselr()
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.modify(|w| w.set_cs(channel_number as _, request))
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});
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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ch.par().write_value(peri_addr as u32);
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ch.mar().write_value(mem_addr as u32);
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ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
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ch.cr().write(|w| {
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w.set_psize(data_size);
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w.set_msize(data_size);
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if incr_mem {
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w.set_minc(vals::Inc::ENABLED);
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} else {
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w.set_minc(vals::Inc::DISABLED);
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}
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w.set_dir(dir);
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w.set_teie(true);
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w.set_tcie(true);
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w.set_en(true);
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});
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}
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pub unsafe fn request_stop(dma: pac::bdma::Dma, channel_number: u8) {
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reset_status(dma, channel_number);
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let ch = dma.ch(channel_number as _);
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// Disable the channel and interrupts with the default value.
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ch.cr().write(|_| ());
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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}
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2021-12-08 01:51:39 +01:00
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pub unsafe fn is_running(dma: pac::bdma::Dma, ch: u8) -> bool {
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2021-11-19 19:15:55 +01:00
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let ch = dma.ch(ch as _);
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ch.cr().read().en()
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}
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/// Gets the total remaining transfers for the channel
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/// Note: this will be zero for transfers that completed without cancellation.
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pub unsafe fn get_remaining_transfers(dma: pac::bdma::Dma, ch: u8) -> u16 {
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// get a handle on the channel itself
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let ch = dma.ch(ch as _);
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// read the remaining transfer count. If this is zero, the transfer completed fully.
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ch.ndtr().read().ndt()
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}
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/// Sets the waker for the specified DMA channel
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2021-12-08 01:54:31 +01:00
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pub unsafe fn set_waker(state_number: usize, waker: &Waker) {
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STATE.ch_wakers[state_number].register(waker);
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2021-11-19 19:15:55 +01:00
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}
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pub unsafe fn reset_status(dma: pac::bdma::Dma, channel_number: u8) {
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dma.ifcr().write(|w| {
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w.set_tcif(channel_number as _, true);
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w.set_teif(channel_number as _, true);
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});
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}
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}
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