210 lines
4.0 KiB
Rust
210 lines
4.0 KiB
Rust
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pub use nrf9160_pac as pac;
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/// The maximum buffer size that the EasyDMA can send/recv in one operation.
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pub const EASY_DMA_SIZE: usize = (1 << 12) - 1;
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pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
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embassy_hal_common::peripherals! {
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// RTC
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RTC0,
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RTC1,
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// WDT
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WDT,
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// UARTE
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UARTE0,
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UARTE1,
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UARTE2,
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UARTE3,
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// TWI
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TWI0,
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TWI1,
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TWI2,
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TWI3,
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// SPI
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SPI0,
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SPI1,
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SPI2,
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SPI3,
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// SAADC
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SAADC,
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// PWM
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PWM0,
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PWM1,
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PWM2,
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PWM3,
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// TIMER
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TIMER0,
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TIMER1,
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TIMER2,
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// GPIOTE
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GPIOTE_CH0,
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GPIOTE_CH1,
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GPIOTE_CH2,
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GPIOTE_CH3,
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GPIOTE_CH4,
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GPIOTE_CH5,
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GPIOTE_CH6,
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GPIOTE_CH7,
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// PPI
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PPI_CH0,
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PPI_CH1,
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PPI_CH2,
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PPI_CH3,
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PPI_CH4,
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PPI_CH5,
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PPI_CH6,
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PPI_CH7,
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PPI_CH8,
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PPI_CH9,
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PPI_CH10,
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PPI_CH11,
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PPI_CH12,
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PPI_CH13,
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PPI_CH14,
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PPI_CH15,
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PPI_GROUP0,
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PPI_GROUP1,
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PPI_GROUP2,
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PPI_GROUP3,
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PPI_GROUP4,
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PPI_GROUP5,
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// GPIO port 0
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P0_00,
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P0_01,
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P0_02,
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P0_03,
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P0_04,
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P0_05,
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P0_06,
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P0_07,
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P0_08,
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P0_09,
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P0_10,
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P0_11,
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P0_12,
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P0_13,
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P0_14,
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P0_15,
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P0_16,
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P0_17,
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P0_18,
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P0_19,
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P0_20,
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P0_21,
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P0_22,
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P0_23,
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P0_24,
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P0_25,
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P0_26,
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P0_27,
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P0_28,
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P0_29,
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P0_30,
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P0_31,
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}
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impl_uarte!(UARTE0, UARTE0_NS, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
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impl_uarte!(UARTE1, UARTE1_NS, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
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impl_uarte!(UARTE2, UARTE2_NS, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
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impl_uarte!(UARTE3, UARTE3_NS, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
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impl_spim!(SPI0, SPIM0_NS, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
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impl_spim!(SPI1, SPIM1_NS, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
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impl_spim!(SPI2, SPIM2_NS, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
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impl_spim!(SPI3, SPIM3_NS, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
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impl_twim!(TWI0, TWIM0_NS, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
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impl_twim!(TWI1, TWIM1_NS, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
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impl_twim!(TWI2, TWIM2_NS, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
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impl_twim!(TWI3, TWIM3_NS, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
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impl_pwm!(PWM0, PWM0_NS, PWM0);
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impl_pwm!(PWM1, PWM1_NS, PWM1);
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impl_pwm!(PWM2, PWM2_NS, PWM2);
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impl_pwm!(PWM3, PWM3_NS, PWM3);
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impl_timer!(TIMER0, TIMER0_NS, TIMER0);
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impl_timer!(TIMER1, TIMER1_NS, TIMER1);
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impl_timer!(TIMER2, TIMER2_NS, TIMER2);
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impl_pin!(P0_00, 0, 0);
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impl_pin!(P0_01, 0, 1);
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impl_pin!(P0_02, 0, 2);
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impl_pin!(P0_03, 0, 3);
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impl_pin!(P0_04, 0, 4);
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impl_pin!(P0_05, 0, 5);
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impl_pin!(P0_06, 0, 6);
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impl_pin!(P0_07, 0, 7);
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impl_pin!(P0_08, 0, 8);
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impl_pin!(P0_09, 0, 9);
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impl_pin!(P0_10, 0, 10);
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impl_pin!(P0_11, 0, 11);
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impl_pin!(P0_12, 0, 12);
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impl_pin!(P0_13, 0, 13);
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impl_pin!(P0_14, 0, 14);
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impl_pin!(P0_15, 0, 15);
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impl_pin!(P0_16, 0, 16);
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impl_pin!(P0_17, 0, 17);
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impl_pin!(P0_18, 0, 18);
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impl_pin!(P0_19, 0, 19);
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impl_pin!(P0_20, 0, 20);
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impl_pin!(P0_21, 0, 21);
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impl_pin!(P0_22, 0, 22);
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impl_pin!(P0_23, 0, 23);
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impl_pin!(P0_24, 0, 24);
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impl_pin!(P0_25, 0, 25);
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impl_pin!(P0_26, 0, 26);
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impl_pin!(P0_27, 0, 27);
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impl_pin!(P0_28, 0, 28);
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impl_pin!(P0_29, 0, 29);
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impl_pin!(P0_30, 0, 30);
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impl_pin!(P0_31, 0, 31);
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pub mod irqs {
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use crate::pac::Interrupt as InterruptEnum;
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use embassy_macros::interrupt_declare as declare;
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declare!(SPU);
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declare!(CLOCK_POWER);
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declare!(UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
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declare!(UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
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declare!(UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
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declare!(UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
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declare!(GPIOTE0);
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declare!(SAADC);
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declare!(TIMER0);
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declare!(TIMER1);
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declare!(TIMER2);
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declare!(RTC0);
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declare!(RTC1);
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declare!(WDT);
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declare!(EGU0);
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declare!(EGU1);
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declare!(EGU2);
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declare!(EGU3);
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declare!(EGU4);
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declare!(EGU5);
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declare!(PWM0);
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declare!(PWM1);
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declare!(PWM2);
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declare!(PDM);
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declare!(PWM3);
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declare!(I2S);
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declare!(IPC);
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declare!(FPU);
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declare!(GPIOTE1);
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declare!(KMU);
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declare!(CRYPTOCELL);
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}
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