2022-02-09 00:31:21 +01:00
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use proc_macro2::TokenStream;
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use quote::{format_ident, quote};
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use std::collections::HashSet;
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2021-05-25 04:17:24 +02:00
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use std::env;
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2021-08-19 23:15:11 +02:00
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use std::fs;
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2021-05-01 03:07:17 +02:00
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use std::path::PathBuf;
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2022-02-09 00:31:21 +01:00
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use stm32_metapac::metadata::METADATA;
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2021-05-01 03:07:17 +02:00
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fn main() {
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2022-01-24 00:24:23 +01:00
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let chip_name = match env::vars()
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.map(|(a, _)| a)
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.filter(|x| x.starts_with("CARGO_FEATURE_STM32"))
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.get_one()
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{
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Ok(x) => x,
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Err(GetOneError::None) => panic!("No stm32xx Cargo feature enabled"),
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Err(GetOneError::Multiple) => panic!("Multiple stm32xx Cargo features enabled"),
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}
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.strip_prefix("CARGO_FEATURE_")
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.unwrap()
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.to_ascii_lowercase();
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2021-05-01 03:07:17 +02:00
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2022-02-09 00:31:21 +01:00
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for p in METADATA.peripherals {
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if let Some(r) = &p.registers {
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println!("cargo:rustc-cfg={}", r.kind);
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println!("cargo:rustc-cfg={}_{}", r.kind, r.version);
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}
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2021-08-19 23:15:11 +02:00
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}
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2022-02-05 03:03:32 +01:00
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// ========
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// Generate singletons
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2021-08-19 23:15:11 +02:00
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let mut singletons: Vec<String> = Vec::new();
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2022-02-09 00:31:21 +01:00
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for p in METADATA.peripherals {
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if let Some(r) = &p.registers {
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match r.kind {
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// Generate singletons per pin, not per port
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"gpio" => {
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println!("{}", p.name);
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let port_letter = p.name.strip_prefix("GPIO").unwrap();
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for pin_num in 0..16 {
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singletons.push(format!("P{}{}", port_letter, pin_num));
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}
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2021-08-19 23:15:11 +02:00
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}
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2022-02-09 00:31:21 +01:00
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// No singleton for these, the HAL handles them specially.
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"exti" => {}
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2021-05-01 03:07:17 +02:00
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2022-02-09 00:31:21 +01:00
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// We *shouldn't* have singletons for these, but the HAL currently requires
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// singletons, for using with RccPeripheral to enable/disable clocks to them.
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"rcc" => {
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if r.version == "h7" {
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singletons.push("MCO1".to_string());
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singletons.push("MCO2".to_string());
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}
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singletons.push(p.name.to_string());
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2021-11-08 23:43:03 +01:00
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}
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2022-02-09 00:31:21 +01:00
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//"dbgmcu" => {}
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//"syscfg" => {}
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//"dma" => {}
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//"bdma" => {}
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//"dmamux" => {}
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// For other peripherals, one singleton per peri
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_ => singletons.push(p.name.to_string()),
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2021-11-08 23:43:03 +01:00
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}
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2021-08-19 23:15:11 +02:00
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}
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2021-05-01 03:07:17 +02:00
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}
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2021-08-19 23:15:11 +02:00
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// One singleton per EXTI line
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for pin_num in 0..16 {
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singletons.push(format!("EXTI{}", pin_num));
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}
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// One singleton per DMA channel
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2022-02-09 00:31:21 +01:00
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for c in METADATA.dma_channels {
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singletons.push(c.name.to_string());
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2021-08-19 23:15:11 +02:00
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}
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2022-02-09 00:31:21 +01:00
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let mut g = TokenStream::new();
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let singleton_tokens: Vec<_> = singletons.iter().map(|s| format_ident!("{}", s)).collect();
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g.extend(quote! {
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embassy_hal_common::peripherals!(#(#singleton_tokens),*);
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});
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2021-08-19 23:15:11 +02:00
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2022-02-09 00:45:52 +01:00
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// ========
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// Generate interrupt declarations
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let mut irqs = Vec::new();
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for irq in METADATA.interrupts {
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irqs.push(format_ident!("{}", irq.name));
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2021-08-19 23:15:11 +02:00
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}
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2022-02-09 00:45:52 +01:00
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g.extend(quote! {
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pub mod interrupt {
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use crate::pac::Interrupt as InterruptEnum;
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#(
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embassy::interrupt::declare!(#irqs);
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)*
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}
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});
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2021-08-19 23:15:11 +02:00
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2022-02-05 03:03:32 +01:00
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// ========
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// Generate DMA IRQs.
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2022-02-09 00:31:21 +01:00
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let mut dma_irqs: HashSet<&str> = HashSet::new();
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let mut bdma_irqs: HashSet<&str> = HashSet::new();
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2022-02-05 03:03:32 +01:00
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2022-02-09 00:31:21 +01:00
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for p in METADATA.peripherals {
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if let Some(r) = &p.registers {
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match r.kind {
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"dma" => {
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for irq in p.interrupts {
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dma_irqs.insert(irq.interrupt);
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}
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}
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"bdma" => {
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for irq in p.interrupts {
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bdma_irqs.insert(irq.interrupt);
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}
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}
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_ => {}
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}
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}
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2022-02-05 03:03:32 +01:00
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}
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2022-02-09 00:31:21 +01:00
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let tokens: Vec<_> = dma_irqs.iter().map(|s| format_ident!("{}", s)).collect();
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g.extend(quote! {
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#(
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#[crate::interrupt]
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unsafe fn #tokens () {
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crate::dma::dma::on_irq();
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}
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)*
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});
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let tokens: Vec<_> = bdma_irqs.iter().map(|s| format_ident!("{}", s)).collect();
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g.extend(quote! {
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#(
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#[crate::interrupt]
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unsafe fn #tokens () {
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crate::dma::bdma::on_irq();
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}
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)*
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});
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2022-02-09 00:58:17 +01:00
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// ========
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// Generate RccPeripheral impls
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for p in METADATA.peripherals {
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if !singletons.contains(&p.name.to_string()) {
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continue;
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}
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if let Some(rcc) = &p.rcc {
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let en = rcc.enable.as_ref().unwrap();
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let rst = match &rcc.reset {
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Some(rst) => {
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let rst_reg = format_ident!("{}", rst.register.to_ascii_lowercase());
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let set_rst_field = format_ident!("set_{}", rst.field.to_ascii_lowercase());
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quote! {
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critical_section::with(|_| unsafe {
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crate::pac::RCC.#rst_reg().modify(|w| w.#set_rst_field(true));
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crate::pac::RCC.#rst_reg().modify(|w| w.#set_rst_field(false));
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});
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}
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}
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None => TokenStream::new(),
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};
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let pname = format_ident!("{}", p.name);
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let clk = format_ident!("{}", rcc.clock.to_ascii_lowercase());
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let en_reg = format_ident!("{}", en.register.to_ascii_lowercase());
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let set_en_field = format_ident!("set_{}", en.field.to_ascii_lowercase());
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g.extend(quote! {
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impl crate::rcc::sealed::RccPeripheral for peripherals::#pname {
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fn frequency() -> crate::time::Hertz {
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critical_section::with(|_| unsafe {
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crate::rcc::get_freqs().#clk
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})
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}
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fn enable() {
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critical_section::with(|_| unsafe {
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crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(true))
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})
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}
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fn disable() {
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critical_section::with(|_| unsafe {
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crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(false));
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})
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}
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fn reset() {
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#rst
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}
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}
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impl crate::rcc::RccPeripheral for peripherals::#pname {}
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});
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}
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2022-02-05 03:03:32 +01:00
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}
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2022-02-09 00:58:17 +01:00
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// ========
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// Generate fns to enable GPIO, DMA in RCC
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for kind in ["dma", "bdma", "dmamux", "gpio"] {
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let mut gg = TokenStream::new();
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for p in METADATA.peripherals {
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if p.registers.is_some() && p.registers.as_ref().unwrap().kind == kind {
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if let Some(rcc) = &p.rcc {
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let en = rcc.enable.as_ref().unwrap();
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let en_reg = format_ident!("{}", en.register.to_ascii_lowercase());
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let set_en_field = format_ident!("set_{}", en.field.to_ascii_lowercase());
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gg.extend(quote! {
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crate::pac::RCC.#en_reg().modify(|w| w.#set_en_field(true));
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})
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}
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}
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}
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let fname = format_ident!("init_{}", kind);
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g.extend(quote! {
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pub unsafe fn #fname(){
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#gg
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}
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})
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2022-02-05 03:03:32 +01:00
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}
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// ========
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// Write generated.rs
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let out_dir = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
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let out_file = out_dir.join("generated.rs").to_string_lossy().to_string();
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2022-02-09 00:31:21 +01:00
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fs::write(out_file, g.to_string()).unwrap();
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2022-02-05 03:03:32 +01:00
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// ========
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// Multicore
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2021-09-21 13:42:27 +02:00
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let mut s = chip_name.split('_');
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let mut chip_name: String = s.next().unwrap().to_string();
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let core_name = if let Some(c) = s.next() {
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if !c.starts_with("CM") {
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chip_name.push('_');
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chip_name.push_str(c);
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None
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} else {
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Some(c)
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}
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} else {
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None
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};
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2021-07-31 07:20:37 +02:00
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2021-09-21 13:42:27 +02:00
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if let Some(core) = core_name {
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println!(
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"cargo:rustc-cfg={}_{}",
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&chip_name[..chip_name.len() - 2],
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core
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);
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2021-07-31 07:20:37 +02:00
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} else {
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2021-09-21 13:42:27 +02:00
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println!("cargo:rustc-cfg={}", &chip_name[..chip_name.len() - 2]);
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2021-07-31 07:20:37 +02:00
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}
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2022-02-05 03:03:32 +01:00
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// ========
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// stm32f3 wildcard features used in RCC
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2022-02-02 20:51:47 +01:00
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if chip_name.starts_with("stm32f3") {
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println!("cargo:rustc-cfg={}x{}", &chip_name[..9], &chip_name[10..11]);
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}
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2022-02-07 23:32:49 +01:00
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// =======
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// Features for targeting groups of chips
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println!("cargo:rustc-cfg={}", &chip_name[..7]); // stm32f4
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println!("cargo:rustc-cfg={}", &chip_name[..9]); // stm32f429
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println!("cargo:rustc-cfg={}x", &chip_name[..8]); // stm32f42x
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println!("cargo:rustc-cfg={}x{}", &chip_name[..7], &chip_name[8..9]); // stm32f4x9
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2022-01-24 00:24:23 +01:00
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// ========
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// Handle time-driver-XXXX features.
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let time_driver = match env::vars()
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.map(|(a, _)| a)
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.filter(|x| x.starts_with("CARGO_FEATURE_TIME_DRIVER_"))
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.get_one()
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{
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Ok(x) => Some(
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x.strip_prefix("CARGO_FEATURE_TIME_DRIVER_")
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.unwrap()
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.to_ascii_lowercase(),
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),
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Err(GetOneError::None) => None,
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Err(GetOneError::Multiple) => panic!("Multiple stm32xx Cargo features enabled"),
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};
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match time_driver.as_ref().map(|x| x.as_ref()) {
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None => {}
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Some("tim2") => println!("cargo:rustc-cfg=time_driver_tim2"),
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Some("tim3") => println!("cargo:rustc-cfg=time_driver_tim3"),
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2022-01-24 00:50:10 +01:00
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Some("tim4") => println!("cargo:rustc-cfg=time_driver_tim4"),
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Some("tim5") => println!("cargo:rustc-cfg=time_driver_tim5"),
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2022-01-24 00:24:23 +01:00
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Some("any") => {
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if singletons.contains(&"TIM2".to_string()) {
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println!("cargo:rustc-cfg=time_driver_tim2");
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} else if singletons.contains(&"TIM3".to_string()) {
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println!("cargo:rustc-cfg=time_driver_tim3");
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2022-01-24 00:50:10 +01:00
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} else if singletons.contains(&"TIM4".to_string()) {
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println!("cargo:rustc-cfg=time_driver_tim4");
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} else if singletons.contains(&"TIM5".to_string()) {
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println!("cargo:rustc-cfg=time_driver_tim5");
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2022-01-24 00:24:23 +01:00
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} else {
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2022-01-24 00:50:10 +01:00
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panic!("time-driver-any requested, but the chip doesn't have TIM2, TIM3, TIM4 or TIM5.")
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2022-01-24 00:24:23 +01:00
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}
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}
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_ => panic!("unknown time_driver {:?}", time_driver),
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}
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// Handle time-driver-XXXX features.
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if env::var("CARGO_FEATURE_TIME_DRIVER_ANY").is_ok() {}
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println!("cargo:rustc-cfg={}", &chip_name[..chip_name.len() - 2]);
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2021-05-01 03:07:17 +02:00
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println!("cargo:rerun-if-changed=build.rs");
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}
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2022-01-24 00:24:23 +01:00
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|
|
|
enum GetOneError {
|
|
|
|
None,
|
|
|
|
Multiple,
|
|
|
|
}
|
|
|
|
|
|
|
|
trait IteratorExt: Iterator {
|
|
|
|
fn get_one(self) -> Result<Self::Item, GetOneError>;
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<T: Iterator> IteratorExt for T {
|
|
|
|
fn get_one(mut self) -> Result<Self::Item, GetOneError> {
|
|
|
|
match self.next() {
|
|
|
|
None => Err(GetOneError::None),
|
|
|
|
Some(res) => match self.next() {
|
|
|
|
Some(_) => Err(GetOneError::Multiple),
|
|
|
|
None => Ok(res),
|
|
|
|
},
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|