2023-10-03 23:34:13 +02:00
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#![macro_use]
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use crate::Peripheral;
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2023-10-04 23:15:08 +02:00
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#[derive(Clone, Copy)]
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pub enum OpAmpGain {
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Mul1,
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Mul2,
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Mul4,
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Mul8,
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Mul16,
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}
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2023-11-05 04:37:22 +01:00
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#[derive(Clone, Copy)]
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pub enum OpAmpSpeed {
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Normal,
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HighSpeed,
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}
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#[cfg(opamp_g4)]
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impl From<OpAmpSpeed> for crate::pac::opamp::vals::OpampCsrOpahsm {
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fn from(v: OpAmpSpeed) -> Self {
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match v {
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OpAmpSpeed::Normal => crate::pac::opamp::vals::OpampCsrOpahsm::NORMAL,
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OpAmpSpeed::HighSpeed => crate::pac::opamp::vals::OpampCsrOpahsm::HIGHSPEED,
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}
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}
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}
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/// OpAmp external outputs, wired to a GPIO pad.
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///
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/// The GPIO output pad is held by this struct to ensure it cannot be used elsewhere.
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///
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/// This struct can also be used as an ADC input.
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pub struct OpAmpOutput<'d, 'p, T: Instance, P: OutputPin<T>> {
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2023-10-03 23:34:13 +02:00
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_inner: &'d OpAmp<'d, T>,
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2023-11-05 04:37:22 +01:00
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_output: &'p mut P,
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2023-10-03 23:34:13 +02:00
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}
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2023-11-05 04:37:22 +01:00
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/// OpAmp internal outputs, wired directly to ADC inputs.
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///
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/// This struct can be used as an ADC input.
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pub struct OpAmpInternalOutput<'d, T: Instance> {
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_inner: &'d OpAmp<'d, T>,
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}
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/// OpAmp driver.
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2023-10-03 23:34:13 +02:00
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pub struct OpAmp<'d, T: Instance> {
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_inner: PeripheralRef<'d, T>,
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}
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impl<'d, T: Instance> OpAmp<'d, T> {
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2023-11-05 04:37:22 +01:00
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/// Create a new driver instance.
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///
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2023-11-18 20:37:56 +01:00
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/// Does not enable the opamp, but does set the speed mode on some families.
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2023-11-05 04:37:22 +01:00
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pub fn new(opamp: impl Peripheral<P = T> + 'd, #[cfg(opamp_g4)] speed: OpAmpSpeed) -> Self {
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2023-10-03 23:34:13 +02:00
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into_ref!(opamp);
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#[cfg(opamp_g4)]
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T::regs().opamp_csr().modify(|w| {
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2023-11-05 04:37:22 +01:00
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w.set_opahsm(speed.into());
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2023-10-03 23:34:13 +02:00
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});
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Self { _inner: opamp }
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}
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2023-11-05 04:37:22 +01:00
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/// Configure the OpAmp as a buffer for the provided input pin,
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2023-11-18 20:37:56 +01:00
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/// outputting to the provided output pin, and enable the opamp.
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2023-11-05 04:37:22 +01:00
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///
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/// The input pin is configured for analogue mode but not consumed,
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/// so it may subsequently be used for ADC or comparator inputs.
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///
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/// The output pin is held within the returned [`OpAmpOutput`] struct,
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/// preventing it being used elsewhere. The `OpAmpOutput` can then be
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2023-11-20 22:17:09 +01:00
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/// directly used as an ADC input. The opamp will be disabled when the
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/// [`OpAmpOutput`] is dropped.
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2023-11-05 04:37:22 +01:00
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pub fn buffer_ext<'a, 'b, IP, OP>(
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&'a mut self,
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in_pin: &IP,
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out_pin: &'b mut OP,
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gain: OpAmpGain,
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) -> OpAmpOutput<'a, 'b, T, OP>
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2023-10-03 23:34:13 +02:00
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where
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2023-11-05 04:37:22 +01:00
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IP: NonInvertingPin<T> + crate::gpio::sealed::Pin,
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OP: OutputPin<T> + crate::gpio::sealed::Pin,
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{
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2023-11-05 04:37:22 +01:00
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in_pin.set_as_analog();
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out_pin.set_as_analog();
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2023-10-04 23:15:08 +02:00
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let (vm_sel, pga_gain) = match gain {
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OpAmpGain::Mul1 => (0b11, 0b00),
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OpAmpGain::Mul2 => (0b10, 0b00),
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OpAmpGain::Mul4 => (0b10, 0b01),
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OpAmpGain::Mul8 => (0b10, 0b10),
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OpAmpGain::Mul16 => (0b10, 0b11),
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};
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2023-10-03 23:34:13 +02:00
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#[cfg(opamp_f3)]
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T::regs().opampcsr().modify(|w| {
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2023-11-05 04:37:22 +01:00
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w.set_vp_sel(in_pin.channel());
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2023-10-04 23:15:08 +02:00
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w.set_vm_sel(vm_sel);
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w.set_pga_gain(pga_gain);
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2023-11-05 04:37:22 +01:00
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w.set_opampen(true);
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2023-10-04 23:15:08 +02:00
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});
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#[cfg(opamp_g4)]
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T::regs().opamp_csr().modify(|w| {
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use crate::pac::opamp::vals::*;
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2023-11-05 04:37:22 +01:00
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w.set_vp_sel(OpampCsrVpSel::from_bits(in_pin.channel()));
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2023-10-04 23:15:08 +02:00
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w.set_vm_sel(OpampCsrVmSel::from_bits(vm_sel));
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w.set_pga_gain(OpampCsrPgaGain::from_bits(pga_gain));
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2023-11-05 04:37:22 +01:00
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w.set_opaintoen(OpampCsrOpaintoen::OUTPUTPIN);
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w.set_opaen(true);
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2023-10-03 23:34:13 +02:00
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});
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OpAmpOutput {
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_inner: self,
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2023-11-05 04:37:22 +01:00
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_output: out_pin,
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2023-10-03 23:34:13 +02:00
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}
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}
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2023-11-05 04:37:22 +01:00
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/// Configure the OpAmp as a buffer for the provided input pin,
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2023-11-18 20:37:56 +01:00
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/// with the output only used internally, and enable the opamp.
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2023-11-05 04:37:22 +01:00
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///
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/// The input pin is configured for analogue mode but not consumed,
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/// so it may be subsequently used for ADC or comparator inputs.
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///
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/// The returned `OpAmpInternalOutput` struct may be used as an ADC input.
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2023-11-20 22:17:09 +01:00
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/// The opamp output will be disabled when it is dropped.
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2023-11-05 04:37:22 +01:00
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#[cfg(opamp_g4)]
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pub fn buffer_int<'a, P>(&'a mut self, pin: &P, gain: OpAmpGain) -> OpAmpInternalOutput<'a, T>
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where
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P: NonInvertingPin<T> + crate::gpio::sealed::Pin,
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{
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pin.set_as_analog();
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let (vm_sel, pga_gain) = match gain {
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OpAmpGain::Mul1 => (0b11, 0b00),
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OpAmpGain::Mul2 => (0b10, 0b00),
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OpAmpGain::Mul4 => (0b10, 0b01),
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OpAmpGain::Mul8 => (0b10, 0b10),
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OpAmpGain::Mul16 => (0b10, 0b11),
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};
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T::regs().opamp_csr().modify(|w| {
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use crate::pac::opamp::vals::*;
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w.set_vp_sel(OpampCsrVpSel::from_bits(pin.channel()));
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w.set_vm_sel(OpampCsrVmSel::from_bits(vm_sel));
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w.set_pga_gain(OpampCsrPgaGain::from_bits(pga_gain));
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w.set_opaintoen(OpampCsrOpaintoen::ADCCHANNEL);
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w.set_opaen(true);
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});
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OpAmpInternalOutput { _inner: self }
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}
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}
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2023-11-20 22:17:09 +01:00
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impl<'d, 'p, T: Instance, P: OutputPin<T>> Drop for OpAmpOutput<'d, 'p, T, P> {
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fn drop(&mut self) {
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#[cfg(opamp_f3)]
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T::regs().opampcsr().modify(|w| {
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w.set_opampen(false);
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});
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#[cfg(opamp_g4)]
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T::regs().opamp_csr().modify(|w| {
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w.set_opaen(false);
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});
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}
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}
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impl<'d, T: Instance> Drop for OpAmpInternalOutput<'d, T> {
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2023-11-05 04:37:22 +01:00
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fn drop(&mut self) {
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#[cfg(opamp_f3)]
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T::regs().opampcsr().modify(|w| {
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w.set_opampen(false);
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});
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#[cfg(opamp_g4)]
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T::regs().opamp_csr().modify(|w| {
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w.set_opaen(false);
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});
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}
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2023-10-03 23:34:13 +02:00
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}
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pub trait Instance: sealed::Instance + 'static {}
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pub(crate) mod sealed {
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pub trait Instance {
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fn regs() -> crate::pac::opamp::Opamp;
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}
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pub trait NonInvertingPin<T: Instance> {
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fn channel(&self) -> u8;
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}
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pub trait InvertingPin<T: Instance> {
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fn channel(&self) -> u8;
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}
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2023-11-05 04:37:22 +01:00
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pub trait OutputPin<T: Instance> {}
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2023-10-03 23:34:13 +02:00
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}
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pub trait NonInvertingPin<T: Instance>: sealed::NonInvertingPin<T> {}
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pub trait InvertingPin<T: Instance>: sealed::InvertingPin<T> {}
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2023-11-05 04:37:22 +01:00
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pub trait OutputPin<T: Instance>: sealed::OutputPin<T> {}
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2023-10-03 23:34:13 +02:00
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2023-11-05 04:37:22 +01:00
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macro_rules! impl_opamp_external_output {
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2023-10-03 23:34:13 +02:00
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($inst:ident, $adc:ident, $ch:expr) => {
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2023-10-21 14:32:04 +02:00
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foreach_adc!(
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($adc, $common_inst:ident, $adc_clock:ident) => {
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2023-11-05 04:37:22 +01:00
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impl<'d, 'p, P: OutputPin<crate::peripherals::$inst>> crate::adc::sealed::AdcPin<crate::peripherals::$adc>
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2023-10-21 14:32:04 +02:00
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for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
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{
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fn channel(&self) -> u8 {
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$ch
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}
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}
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2023-11-05 04:37:22 +01:00
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impl<'d, 'p, P: OutputPin<crate::peripherals::$inst>> crate::adc::AdcPin<crate::peripherals::$adc>
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2023-10-21 14:32:04 +02:00
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for OpAmpOutput<'d, 'p, crate::peripherals::$inst, P>
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{
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}
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};
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);
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2023-10-03 23:34:13 +02:00
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};
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}
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foreach_peripheral!(
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(opamp, OPAMP1) => {
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2023-11-05 04:37:22 +01:00
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impl_opamp_external_output!(OPAMP1, ADC1, 3);
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};
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(opamp, OPAMP2) => {
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impl_opamp_external_output!(OPAMP2, ADC2, 3);
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};
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(opamp, OPAMP3) => {
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impl_opamp_external_output!(OPAMP3, ADC3, 1);
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};
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// OPAMP4 only in STM32G4 Cat 3 devices
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(opamp, OPAMP4) => {
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impl_opamp_external_output!(OPAMP4, ADC4, 3);
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};
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// OPAMP5 only in STM32G4 Cat 3 devices
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(opamp, OPAMP5) => {
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impl_opamp_external_output!(OPAMP5, ADC5, 1);
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};
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// OPAMP6 only in STM32G4 Cat 3/4 devices
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(opamp, OPAMP6) => {
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impl_opamp_external_output!(OPAMP6, ADC1, 14);
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};
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);
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#[cfg(opamp_g4)]
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macro_rules! impl_opamp_internal_output {
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($inst:ident, $adc:ident, $ch:expr) => {
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foreach_adc!(
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($adc, $common_inst:ident, $adc_clock:ident) => {
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impl<'d> crate::adc::sealed::AdcPin<crate::peripherals::$adc>
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for OpAmpInternalOutput<'d, crate::peripherals::$inst>
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{
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fn channel(&self) -> u8 {
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$ch
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}
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}
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impl<'d> crate::adc::AdcPin<crate::peripherals::$adc>
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for OpAmpInternalOutput<'d, crate::peripherals::$inst>
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{
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}
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};
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);
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};
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}
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#[cfg(opamp_g4)]
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foreach_peripheral!(
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(opamp, OPAMP1) => {
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impl_opamp_internal_output!(OPAMP1, ADC1, 13);
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};
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(opamp, OPAMP2) => {
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impl_opamp_internal_output!(OPAMP2, ADC2, 16);
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};
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(opamp, OPAMP3) => {
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impl_opamp_internal_output!(OPAMP3, ADC2, 18);
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// Only in Cat 3/4 devices
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impl_opamp_internal_output!(OPAMP3, ADC3, 13);
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2023-10-03 23:34:13 +02:00
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};
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// OPAMP4 only in Cat 3 devices
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(opamp, OPAMP4) => {
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2023-11-05 04:37:22 +01:00
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impl_opamp_internal_output!(OPAMP4, ADC5, 5);
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};
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// OPAMP5 only in Cat 3 devices
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(opamp, OPAMP5) => {
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impl_opamp_internal_output!(OPAMP5, ADC5, 3);
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};
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// OPAMP6 only in Cat 3/4 devices
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(opamp, OPAMP6) => {
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// Only in Cat 3 devices
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impl_opamp_internal_output!(OPAMP6, ADC4, 17);
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// Only in Cat 4 devices
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impl_opamp_internal_output!(OPAMP6, ADC3, 17);
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2023-10-03 23:34:13 +02:00
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};
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);
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foreach_peripheral! {
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(opamp, $inst:ident) => {
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impl sealed::Instance for crate::peripherals::$inst {
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fn regs() -> crate::pac::opamp::Opamp {
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crate::pac::$inst
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}
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}
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impl Instance for crate::peripherals::$inst {
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}
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};
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}
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#[allow(unused_macros)]
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2023-11-05 04:37:22 +01:00
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macro_rules! impl_opamp_vp_pin {
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2023-10-03 23:34:13 +02:00
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($inst:ident, $pin:ident, $ch:expr) => {
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impl crate::opamp::NonInvertingPin<peripherals::$inst> for crate::peripherals::$pin {}
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impl crate::opamp::sealed::NonInvertingPin<peripherals::$inst> for crate::peripherals::$pin {
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fn channel(&self) -> u8 {
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|
$ch
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}
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}
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};
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}
|
2023-11-05 04:37:22 +01:00
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#[allow(unused_macros)]
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|
|
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macro_rules! impl_opamp_vout_pin {
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|
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($inst:ident, $pin:ident) => {
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|
|
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impl crate::opamp::OutputPin<peripherals::$inst> for crate::peripherals::$pin {}
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|
|
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impl crate::opamp::sealed::OutputPin<peripherals::$inst> for crate::peripherals::$pin {}
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};
|
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}
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