351 lines
10 KiB
Rust
351 lines
10 KiB
Rust
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use core::marker::PhantomData;
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use core::pin::Pin;
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use core::sync::atomic::{fence, Ordering};
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use embassy::util::{AtomicWaker, Unborrow};
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use embassy_extras::peripheral::{PeripheralMutex, PeripheralState};
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use embassy_extras::unborrow;
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use embassy_net::MTU;
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use crate::gpio::sealed::Pin as __GpioPin;
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use crate::gpio::AnyPin;
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use crate::gpio::Pin as GpioPin;
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use crate::interrupt::Interrupt;
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use crate::pac::gpio::vals::Ospeedr;
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use crate::pac::ETH;
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use crate::peripherals;
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mod descriptors;
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use descriptors::DescriptorRing;
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/// Station Management Interface (SMI) on an ethernet PHY
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pub trait StationManagement {
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/// Read a register over SMI.
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fn smi_read(&mut self, reg: u8) -> u16;
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/// Write a register over SMI.
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fn smi_write(&mut self, reg: u8, val: u16);
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}
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/// Traits for an Ethernet PHY
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pub trait PHY {
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/// Reset PHY and wait for it to come out of reset.
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fn phy_reset(&mut self);
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/// PHY initialisation.
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fn phy_init(&mut self);
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}
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pub struct Ethernet<'d, T: Instance, const TX: usize, const RX: usize> {
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state: PeripheralMutex<Inner<'d, T, TX, RX>>,
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pins: [AnyPin; 9],
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}
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impl<'d, T: Instance, const TX: usize, const RX: usize> Ethernet<'d, T, TX, RX> {
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pub fn new(
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peri: impl Unborrow<Target = T> + 'd,
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interrupt: impl Unborrow<Target = T::Interrupt> + 'd,
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ref_clk: impl Unborrow<Target = impl RefClkPin<T>> + 'd,
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mdio: impl Unborrow<Target = impl MDIOPin<T>> + 'd,
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mdc: impl Unborrow<Target = impl MDCPin<T>> + 'd,
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crs: impl Unborrow<Target = impl CRSPin<T>> + 'd,
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rx_d0: impl Unborrow<Target = impl RXD0Pin<T>> + 'd,
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rx_d1: impl Unborrow<Target = impl RXD1Pin<T>> + 'd,
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tx_d0: impl Unborrow<Target = impl TXD0Pin<T>> + 'd,
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tx_d1: impl Unborrow<Target = impl TXD1Pin<T>> + 'd,
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tx_en: impl Unborrow<Target = impl TXEnPin<T>> + 'd,
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mac_addr: [u8; 6],
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) -> Self {
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unborrow!(interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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ref_clk.configure();
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mdio.configure();
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mdc.configure();
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crs.configure();
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rx_d0.configure();
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rx_d1.configure();
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tx_d0.configure();
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tx_d1.configure();
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tx_en.configure();
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let inner = Inner::new(peri);
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let state = PeripheralMutex::new(inner, interrupt);
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// NOTE(unsafe) We have exclusive access to the registers
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unsafe {
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let dma = ETH.ethernet_dma();
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let mac = ETH.ethernet_mac();
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let mtl = ETH.ethernet_mtl();
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// Reset and wait
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dma.dmamr().modify(|w| w.set_swr(true));
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while dma.dmamr().read().swr() {}
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// 200 MHz ?
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mac.mac1ustcr().modify(|w| w.set_tic_1us_cntr(200 - 1));
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mac.maccr().modify(|w| {
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w.set_ipg(0b000); // 96 bit times
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w.set_acs(true);
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w.set_fes(true);
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w.set_dm(true);
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// TODO: Carrier sense ? ECRSFD
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});
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mac.maca0lr().write(|w| {
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w.set_addrlo(
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u32::from(mac_addr[0])
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| (u32::from(mac_addr[1]) << 8)
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| (u32::from(mac_addr[2]) << 16)
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| (u32::from(mac_addr[3]) << 24),
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)
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});
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mac.maca0hr()
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.modify(|w| w.set_addrhi(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
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// TODO: Enable filtering once we get the basics working
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mac.macpfr().modify(|w| w.set_ra(true));
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mac.macqtx_fcr().modify(|w| w.set_pt(0x100));
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mtl.mtlrx_qomr().modify(|w| w.set_rsf(true));
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mtl.mtltx_qomr().modify(|w| w.set_tsf(true));
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// TODO: Address aligned beats plus fixed burst ?
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dma.dmactx_cr().modify(|w| w.set_txpbl(1)); // 32 ?
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dma.dmacrx_cr().modify(|w| {
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w.set_rxpbl(1); // 32 ?
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w.set_rbsz(MTU as u16);
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});
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}
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let pins = [
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ref_clk.degrade(),
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mdio.degrade(),
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mdc.degrade(),
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crs.degrade(),
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rx_d0.degrade(),
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rx_d1.degrade(),
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tx_d0.degrade(),
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tx_d1.degrade(),
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tx_en.degrade(),
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];
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Self { state, pins }
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}
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pub fn init(self: Pin<&mut Self>) {
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// NOTE(unsafe) We won't move this
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let this = unsafe { self.get_unchecked_mut() };
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let mutex = unsafe { Pin::new_unchecked(&mut this.state) };
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mutex.with(|s, _| {
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s.desc_ring.init();
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fence(Ordering::SeqCst);
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unsafe {
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let mac = ETH.ethernet_mac();
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let mtl = ETH.ethernet_mtl();
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let dma = ETH.ethernet_dma();
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mac.maccr().modify(|w| {
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w.set_re(true);
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w.set_te(true);
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});
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mtl.mtltx_qomr().modify(|w| w.set_ftq(true));
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dma.dmactx_cr().modify(|w| w.set_st(true));
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dma.dmacrx_cr().modify(|w| w.set_sr(true));
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// Enable interrupts
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dma.dmacier().modify(|w| {
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w.set_nie(true);
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w.set_rie(true);
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w.set_tie(true);
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});
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}
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});
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}
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}
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impl<'d, T: Instance, const TX: usize, const RX: usize> Drop for Ethernet<'d, T, TX, RX> {
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fn drop(&mut self) {
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for pin in self.pins.iter_mut() {
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// NOTE(unsafe) Exclusive access to the regs
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critical_section::with(|_| unsafe {
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pin.set_as_analog();
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pin.block()
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.ospeedr()
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.modify(|w| w.set_ospeedr(pin.pin() as usize, Ospeedr::LOWSPEED));
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})
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}
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}
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}
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//----------------------------------------------------------------------
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struct Inner<'d, T: Instance, const TX: usize, const RX: usize> {
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_peri: PhantomData<&'d mut T>,
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desc_ring: DescriptorRing<TX, RX>,
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}
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impl<'d, T: Instance, const TX: usize, const RX: usize> Inner<'d, T, TX, RX> {
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pub fn new(_peri: impl Unborrow<Target = T> + 'd) -> Self {
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Self {
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_peri: PhantomData,
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desc_ring: DescriptorRing::new(),
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}
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}
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}
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impl<'d, T: Instance, const TX: usize, const RX: usize> PeripheralState for Inner<'d, T, TX, RX> {
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type Interrupt = T::Interrupt;
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fn on_interrupt(&mut self) {
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unwrap!(self.desc_ring.tx.on_interrupt());
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self.desc_ring.rx.on_interrupt();
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T::state().wake();
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// TODO: Check and clear more flags
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmacsr().modify(|w| {
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w.set_ti(false);
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w.set_ri(false);
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});
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// Delay two peripheral's clock
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dma.dmacsr().read();
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dma.dmacsr().read();
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}
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}
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}
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mod sealed {
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use super::*;
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pub trait Instance {
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type Interrupt: Interrupt;
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fn state() -> &'static AtomicWaker;
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}
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pub trait RefClkPin<T: Instance>: GpioPin {
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fn configure(&mut self);
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}
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pub trait MDIOPin<T: Instance>: GpioPin {
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fn configure(&mut self);
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}
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pub trait MDCPin<T: Instance>: GpioPin {
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fn configure(&mut self);
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}
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pub trait CRSPin<T: Instance>: GpioPin {
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fn configure(&mut self);
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}
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pub trait RXD0Pin<T: Instance>: GpioPin {
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fn configure(&mut self);
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}
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pub trait RXD1Pin<T: Instance>: GpioPin {
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fn configure(&mut self);
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}
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pub trait TXD0Pin<T: Instance>: GpioPin {
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fn configure(&mut self);
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}
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pub trait TXD1Pin<T: Instance>: GpioPin {
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fn configure(&mut self);
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}
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pub trait TXEnPin<T: Instance>: GpioPin {
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fn configure(&mut self);
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}
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}
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pub trait Instance: sealed::Instance + 'static {}
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pub trait RefClkPin<T: Instance>: sealed::RefClkPin<T> + 'static {}
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pub trait MDIOPin<T: Instance>: sealed::MDIOPin<T> + 'static {}
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pub trait MDCPin<T: Instance>: sealed::MDCPin<T> + 'static {}
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pub trait CRSPin<T: Instance>: sealed::CRSPin<T> + 'static {}
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pub trait RXD0Pin<T: Instance>: sealed::RXD0Pin<T> + 'static {}
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pub trait RXD1Pin<T: Instance>: sealed::RXD1Pin<T> + 'static {}
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pub trait TXD0Pin<T: Instance>: sealed::TXD0Pin<T> + 'static {}
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pub trait TXD1Pin<T: Instance>: sealed::TXD1Pin<T> + 'static {}
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pub trait TXEnPin<T: Instance>: sealed::TXEnPin<T> + 'static {}
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crate::pac::peripherals!(
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(eth, $inst:ident) => {
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impl sealed::Instance for peripherals::$inst {
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type Interrupt = crate::interrupt::$inst;
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fn state() -> &'static AtomicWaker {
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static WAKER: AtomicWaker = AtomicWaker::new();
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&WAKER
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}
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}
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impl Instance for peripherals::$inst {}
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};
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);
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macro_rules! impl_pin {
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($inst:ident, $pin:ident, $signal:ident, $af:expr) => {
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impl sealed::$signal<peripherals::$inst> for peripherals::$pin {
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fn configure(&mut self) {
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// NOTE(unsafe) Exclusive access to the registers
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critical_section::with(|_| unsafe {
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self.set_as_af($af);
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self.block()
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.ospeedr()
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.modify(|w| w.set_ospeedr(self.pin() as usize, Ospeedr::VERYHIGHSPEED));
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})
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}
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}
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impl $signal<peripherals::$inst> for peripherals::$pin {}
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};
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}
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crate::pac::peripheral_pins!(
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($inst:ident, eth, ETH, $pin:ident, REF_CLK, $af:expr) => {
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impl_pin!($inst, $pin, RefClkPin, $af);
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};
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($inst:ident, eth, ETH, $pin:ident, MDIO, $af:expr) => {
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impl_pin!($inst, $pin, MDIOPin, $af);
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};
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($inst:ident, eth, ETH, $pin:ident, MDC, $af:expr) => {
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impl_pin!($inst, $pin, MDCPin, $af);
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};
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($inst:ident, eth, ETH, $pin:ident, CRS_DV, $af:expr) => {
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impl_pin!($inst, $pin, CRSPin, $af);
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};
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($inst:ident, eth, ETH, $pin:ident, RXD0, $af:expr) => {
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impl_pin!($inst, $pin, RXD0Pin, $af);
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};
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($inst:ident, eth, ETH, $pin:ident, RXD1, $af:expr) => {
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impl_pin!($inst, $pin, RXD1Pin, $af);
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};
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($inst:ident, eth, ETH, $pin:ident, TXD0, $af:expr) => {
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impl_pin!($inst, $pin, TXD0Pin, $af);
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};
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($inst:ident, eth, ETH, $pin:ident, TXD1, $af:expr) => {
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impl_pin!($inst, $pin, TXD1Pin, $af);
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};
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($inst:ident, eth, ETH, $pin:ident, TX_EN, $af:expr) => {
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impl_pin!($inst, $pin, TXEnPin, $af);
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};
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);
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