2021-06-10 21:33:43 +02:00
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#![no_std]
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#![no_main]
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2021-07-03 14:05:12 +02:00
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#![allow(incomplete_features)]
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2021-06-10 21:33:43 +02:00
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#![feature(trait_alias)]
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#![feature(min_type_alias_impl_trait)]
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#![feature(impl_trait_in_bindings)]
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#![feature(type_alias_impl_trait)]
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#[path = "../example_common.rs"]
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mod example_common;
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use example_common::*;
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use cortex_m::delay::Delay;
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2021-07-23 14:24:38 +02:00
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use cortex_m_rt::entry;
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2021-06-10 21:33:43 +02:00
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use embassy_stm32::adc::{Adc, Resolution};
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2021-07-23 14:24:38 +02:00
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use embassy_stm32::pac;
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2021-07-03 14:05:12 +02:00
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use stm32l4xx_hal::prelude::*;
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2021-07-05 03:09:42 +02:00
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use stm32l4xx_hal::rcc::PllSource;
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2021-06-10 21:33:43 +02:00
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#[entry]
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fn main() -> ! {
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info!("Hello World, dude!");
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//let pp = pac::Peripherals::take().unwrap();
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let cp = cortex_m::Peripherals::take().unwrap();
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let pp = stm32l4xx_hal::stm32::Peripherals::take().unwrap();
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let mut flash = pp.FLASH.constrain();
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let mut rcc = pp.RCC.constrain();
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let mut pwr = pp.PWR.constrain(&mut rcc.apb1r1);
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2021-07-05 03:09:42 +02:00
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let mut delay = Delay::new(cp.SYST, 80_000_000);
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2021-06-10 21:33:43 +02:00
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// TRY the other clock configuration
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// let clocks = rcc.cfgr.freeze(&mut flash.acr);
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2021-07-05 03:09:42 +02:00
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rcc.cfgr
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2021-06-10 21:33:43 +02:00
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.sysclk(80.mhz())
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.pclk1(80.mhz())
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.pclk2(80.mhz())
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.pll_source(PllSource::HSI16)
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.freeze(&mut flash.acr, &mut pwr);
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2021-07-23 14:24:38 +02:00
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unsafe {
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pac::RCC.ccipr().modify(|w| {
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w.set_adcsel(0b11);
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});
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pac::DBGMCU.cr().modify(|w| {
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w.set_dbg_sleep(true);
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w.set_dbg_standby(true);
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w.set_dbg_stop(true);
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});
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}
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2021-06-10 21:33:43 +02:00
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let p = embassy_stm32::init(Default::default());
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2021-07-05 03:09:42 +02:00
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let mut adc = Adc::new(p.ADC1, &mut delay);
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2021-06-10 21:33:43 +02:00
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//adc.enable_vref();
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adc.set_resolution(Resolution::EightBit);
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let mut channel = p.PC0;
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loop {
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let v = adc.read(&mut channel);
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info!("--> {}", v);
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}
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}
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