2022-11-15 16:12:07 +01:00
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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2023-07-28 13:23:22 +02:00
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use embassy_hal_internal::{into_ref, PeripheralRef};
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2022-11-15 16:12:07 +01:00
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use embassy_sync::waitqueue::AtomicWaker;
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2023-07-05 20:05:34 +02:00
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use crate::gpio::sealed::Pin as GpioPin;
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use crate::gpio::{self, AnyPin, Pull};
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2023-06-08 16:08:40 +02:00
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use crate::interrupt::typelevel::Binding;
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use crate::interrupt::InterruptExt;
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2022-11-15 16:12:07 +01:00
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use crate::peripherals::ADC;
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2023-06-08 16:08:40 +02:00
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use crate::{interrupt, pac, peripherals, Peripheral};
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2022-11-15 16:12:07 +01:00
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2023-07-05 20:05:34 +02:00
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static WAKER: AtomicWaker = AtomicWaker::new();
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2022-11-15 16:12:07 +01:00
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#[non_exhaustive]
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pub struct Config {}
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impl Default for Config {
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fn default() -> Self {
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Self {}
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}
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}
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2023-07-05 20:05:34 +02:00
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pub struct Pin<'p> {
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pin: PeripheralRef<'p, AnyPin>,
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}
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impl<'p> Pin<'p> {
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pub fn new(pin: impl Peripheral<P = impl AdcPin + 'p> + 'p, pull: Pull) -> Self {
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into_ref!(pin);
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pin.pad_ctrl().modify(|w| {
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// manual says:
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//
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// > When using an ADC input shared with a GPIO pin, the pin’s
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// > digital functions must be disabled by setting IE low and OD
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// > high in the pin’s pad control register
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w.set_ie(false);
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w.set_od(true);
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w.set_pue(pull == Pull::Up);
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w.set_pde(pull == Pull::Down);
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});
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Self { pin: pin.map_into() }
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}
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fn channel(&self) -> u8 {
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// this requires adc pins to be sequential and matching the adc channels,
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// which is the case for rp2040
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self.pin._pin() - 26
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}
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}
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impl<'d> Drop for Pin<'d> {
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fn drop(&mut self) {
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self.pin.pad_ctrl().modify(|w| {
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w.set_ie(true);
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w.set_od(false);
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w.set_pue(false);
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w.set_pde(true);
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});
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}
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}
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#[derive(Debug, Eq, PartialEq, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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ConversionFailed,
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}
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pub trait Mode {}
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pub struct Async;
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impl Mode for Async {}
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pub struct Blocking;
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impl Mode for Blocking {}
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pub struct Adc<'d, M: Mode> {
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phantom: PhantomData<(&'d ADC, M)>,
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2022-11-15 16:12:07 +01:00
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}
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2023-07-20 15:48:59 +02:00
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impl<'d, M: Mode> Drop for Adc<'d, M> {
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fn drop(&mut self) {
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let r = Self::regs();
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// disable ADC. leaving it enabled comes with a ~150µA static
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// current draw. the temperature sensor has already been disabled
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// by the temperature-reading methods, so we don't need to touch that.
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r.cs().write(|w| w.set_en(false));
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}
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}
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2023-07-05 20:05:34 +02:00
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impl<'d, M: Mode> Adc<'d, M> {
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2022-11-15 16:12:07 +01:00
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#[inline]
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fn regs() -> pac::adc::Adc {
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pac::ADC
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}
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#[inline]
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fn reset() -> pac::resets::regs::Peripherals {
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let mut ret = pac::resets::regs::Peripherals::default();
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ret.set_adc(true);
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ret
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}
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2023-07-05 20:05:34 +02:00
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fn setup() {
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2023-06-16 01:32:18 +02:00
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let reset = Self::reset();
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crate::reset::reset(reset);
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crate::reset::unreset_wait(reset);
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let r = Self::regs();
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// Enable ADC
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r.cs().write(|w| w.set_en(true));
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// Wait for ADC ready
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while !r.cs().read().ready() {}
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2023-07-05 20:05:34 +02:00
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}
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fn sample_blocking(channel: u8) -> Result<u16, Error> {
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let r = Self::regs();
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r.cs().modify(|w| {
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w.set_ainsel(channel);
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w.set_start_once(true);
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w.set_err(true);
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});
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while !r.cs().read().ready() {}
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match r.cs().read().err() {
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true => Err(Error::ConversionFailed),
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false => Ok(r.result().read().result().into()),
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}
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}
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pub fn blocking_read(&mut self, pin: &mut Pin) -> Result<u16, Error> {
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Self::sample_blocking(pin.channel())
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}
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pub fn blocking_read_temperature(&mut self) -> Result<u16, Error> {
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let r = Self::regs();
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r.cs().modify(|w| w.set_ts_en(true));
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while !r.cs().read().ready() {}
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let result = Self::sample_blocking(4);
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r.cs().modify(|w| w.set_ts_en(false));
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result
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}
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}
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impl<'d> Adc<'d, Async> {
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pub fn new(
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_inner: impl Peripheral<P = ADC> + 'd,
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_irq: impl Binding<interrupt::typelevel::ADC_IRQ_FIFO, InterruptHandler>,
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_config: Config,
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) -> Self {
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Self::setup();
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2022-11-15 16:12:07 +01:00
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// Setup IRQ
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2023-06-08 16:08:40 +02:00
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interrupt::ADC_IRQ_FIFO.unpend();
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unsafe { interrupt::ADC_IRQ_FIFO.enable() };
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2022-11-15 16:12:07 +01:00
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Self { phantom: PhantomData }
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}
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async fn wait_for_ready() {
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let r = Self::regs();
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2023-06-16 01:32:18 +02:00
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r.inte().write(|w| w.set_fifo(true));
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compiler_fence(Ordering::SeqCst);
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poll_fn(|cx| {
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WAKER.register(cx.waker());
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if r.cs().read().ready() {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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2022-11-15 16:12:07 +01:00
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}
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2023-07-05 20:05:34 +02:00
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async fn sample_async(channel: u8) -> Result<u16, Error> {
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2022-11-15 16:12:07 +01:00
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let r = Self::regs();
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2023-06-16 01:32:18 +02:00
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r.cs().modify(|w| {
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2023-07-05 20:05:34 +02:00
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w.set_ainsel(channel);
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w.set_start_once(true);
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w.set_err(true);
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2023-06-16 01:32:18 +02:00
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});
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Self::wait_for_ready().await;
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2023-07-05 20:05:34 +02:00
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match r.cs().read().err() {
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true => Err(Error::ConversionFailed),
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false => Ok(r.result().read().result().into()),
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}
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2022-11-15 16:12:07 +01:00
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}
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2023-07-05 20:05:34 +02:00
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pub async fn read(&mut self, pin: &mut Pin<'_>) -> Result<u16, Error> {
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Self::sample_async(pin.channel()).await
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}
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pub async fn read_temperature(&mut self) -> Result<u16, Error> {
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2022-11-15 16:12:07 +01:00
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let r = Self::regs();
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2023-06-16 01:32:18 +02:00
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r.cs().modify(|w| w.set_ts_en(true));
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if !r.cs().read().ready() {
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2022-11-15 16:12:07 +01:00
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Self::wait_for_ready().await;
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}
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2023-07-05 20:05:34 +02:00
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let result = Self::sample_async(4).await;
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r.cs().modify(|w| w.set_ts_en(false));
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result
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2022-11-15 16:12:07 +01:00
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}
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2023-07-05 20:05:34 +02:00
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}
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2022-11-15 16:12:07 +01:00
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2023-07-05 20:05:34 +02:00
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impl<'d> Adc<'d, Blocking> {
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pub fn new_blocking(_inner: impl Peripheral<P = ADC> + 'd, _config: Config) -> Self {
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Self::setup();
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2022-11-15 16:12:07 +01:00
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2023-07-05 20:05:34 +02:00
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Self { phantom: PhantomData }
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2022-11-15 16:12:07 +01:00
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}
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}
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2023-05-15 15:21:05 +02:00
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pub struct InterruptHandler {
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_empty: (),
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}
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2023-06-08 16:08:40 +02:00
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impl interrupt::typelevel::Handler<interrupt::typelevel::ADC_IRQ_FIFO> for InterruptHandler {
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2023-05-15 15:21:05 +02:00
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unsafe fn on_interrupt() {
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2023-07-05 20:05:34 +02:00
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let r = Adc::<Async>::regs();
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2023-05-15 15:21:05 +02:00
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r.inte().write(|w| w.set_fifo(false));
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WAKER.wake();
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}
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}
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2023-07-05 20:05:34 +02:00
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mod sealed {
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2023-07-21 21:01:56 +02:00
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pub trait AdcChannel {
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2023-07-05 20:05:34 +02:00
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fn channel(&mut self) -> u8;
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}
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}
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2023-07-21 21:01:56 +02:00
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pub trait AdcChannel: sealed::AdcChannel {}
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pub trait AdcPin: AdcChannel + gpio::Pin {}
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2023-07-05 20:05:34 +02:00
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macro_rules! impl_pin {
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($pin:ident, $channel:expr) => {
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2023-07-21 21:01:56 +02:00
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impl sealed::AdcChannel for peripherals::$pin {
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2023-07-05 20:05:34 +02:00
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fn channel(&mut self) -> u8 {
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$channel
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}
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}
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2023-07-21 21:01:56 +02:00
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impl AdcChannel for peripherals::$pin {}
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2023-07-05 20:05:34 +02:00
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impl AdcPin for peripherals::$pin {}
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};
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}
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2022-11-15 16:12:07 +01:00
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impl_pin!(PIN_26, 0);
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impl_pin!(PIN_27, 1);
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impl_pin!(PIN_28, 2);
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impl_pin!(PIN_29, 3);
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