607 lines
17 KiB
Rust
607 lines
17 KiB
Rust
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use core::marker::PhantomData;
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use stm32_metapac::rcc::vals::{Hpre, Ppre, Timpre};
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use crate::pac::pwr::vals::Vos;
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use crate::pac::rcc::vals::{Hseext, Hsidiv, Mco1, Mco2, Pllrge, Pllsrc, Pllvcosel, Sw};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::{peripherals, Peripheral};
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(64_000_000);
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/// CSI speed
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pub const CSI_FREQ: Hertz = Hertz(4_000_000);
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/// HSI48 speed
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pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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const VCO_MIN: u32 = 150_000_000;
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const VCO_MAX: u32 = 420_000_000;
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const VCO_WIDE_MIN: u32 = 128_000_000;
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const VCO_WIDE_MAX: u32 = 560_000_000;
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/// Voltage Scale
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///
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/// Represents the voltage range feeding the CPU core. The maximum core
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/// clock frequency depends on this value.
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#[derive(Copy, Clone, PartialEq)]
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pub enum VoltageScale {
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/// VOS 0 range VCORE 1.30V - 1.40V
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Scale0,
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/// VOS 1 range VCORE 1.15V - 1.26V
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Scale1,
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/// VOS 2 range VCORE 1.05V - 1.15V
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Scale2,
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/// VOS 3 range VCORE 0.95V - 1.05V
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Scale3,
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}
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
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BypassAnalog,
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/// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
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BypassDigital,
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}
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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pub enum Hsi {
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/// 64Mhz
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Mhz64,
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/// 32Mhz (divided by 2)
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Mhz32,
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/// 16Mhz (divided by 4)
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Mhz16,
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/// 8Mhz (divided by 8)
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Mhz8,
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}
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pub enum Sysclk {
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/// HSI selected as sysclk
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HSI,
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/// HSE selected as sysclk
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HSE,
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/// CSI selected as sysclk
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CSI,
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/// PLL1_P selected as sysclk
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Pll1P,
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}
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pub enum PllSource {
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Hsi,
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Csi,
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Hse,
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}
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pub struct Pll {
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/// Source clock selection.
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pub source: PllSource,
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/// PLL pre-divider (DIVM). Must be between 1 and 63.
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pub prediv: u8,
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/// PLL multiplication factor. Must be between 4 and 512.
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pub mul: u16,
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/// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
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/// On PLL1, it must be even (in particular, it cannot be 1.)
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pub divp: Option<u16>,
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/// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
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pub divq: Option<u16>,
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/// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
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pub divr: Option<u16>,
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}
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/// AHB prescaler
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#[derive(Clone, Copy, PartialEq)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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impl AHBPrescaler {
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fn div(&self, clk: Hertz) -> Hertz {
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match self {
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Self::NotDivided => clk,
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Self::Div2 => clk / 2u32,
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Self::Div4 => clk / 4u32,
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Self::Div8 => clk / 8u32,
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Self::Div16 => clk / 16u32,
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Self::Div64 => clk / 64u32,
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Self::Div128 => clk / 128u32,
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Self::Div256 => clk / 256u32,
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Self::Div512 => clk / 512u32,
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}
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}
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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impl APBPrescaler {
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fn div(&self, clk: Hertz) -> Hertz {
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match self {
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Self::NotDivided => clk,
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Self::Div2 => clk / 2u32,
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Self::Div4 => clk / 4u32,
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Self::Div8 => clk / 8u32,
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Self::Div16 => clk / 16u32,
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}
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}
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fn div_tim(&self, clk: Hertz, tim: TimerPrescaler) -> Hertz {
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match (tim, self) {
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// The timers kernel clock is equal to rcc_hclk1 if PPRE1 or PPRE2 corresponds to a
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// division by 1 or 2, else it is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2
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(TimerPrescaler::DefaultX2, Self::NotDivided) => clk,
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(TimerPrescaler::DefaultX2, Self::Div2) => clk,
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(TimerPrescaler::DefaultX2, Self::Div4) => clk / 2u32,
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(TimerPrescaler::DefaultX2, Self::Div8) => clk / 4u32,
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(TimerPrescaler::DefaultX2, Self::Div16) => clk / 8u32,
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// The timers kernel clock is equal to 2 x Frcc_pclk1 or 2 x Frcc_pclk2 if PPRE1 or PPRE2
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// corresponds to a division by 1, 2 or 4, else it is equal to 4 x Frcc_pclk1 or 4 x Frcc_pclk2
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// this makes NO SENSE and is different than in the H7. Mistake in the RM??
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(TimerPrescaler::DefaultX4, Self::NotDivided) => clk * 2u32,
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(TimerPrescaler::DefaultX4, Self::Div2) => clk,
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(TimerPrescaler::DefaultX4, Self::Div4) => clk / 2u32,
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(TimerPrescaler::DefaultX4, Self::Div8) => clk / 2u32,
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(TimerPrescaler::DefaultX4, Self::Div16) => clk / 4u32,
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}
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}
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum TimerPrescaler {
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DefaultX2,
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DefaultX4,
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}
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impl From<TimerPrescaler> for Timpre {
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fn from(value: TimerPrescaler) -> Self {
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match value {
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TimerPrescaler::DefaultX2 => Timpre::DEFAULTX2,
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TimerPrescaler::DefaultX4 => Timpre::DEFAULTX4,
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}
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}
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}
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impl From<APBPrescaler> for Ppre {
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fn from(val: APBPrescaler) -> Ppre {
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match val {
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APBPrescaler::NotDivided => Ppre::DIV1,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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impl From<AHBPrescaler> for Hpre {
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fn from(val: AHBPrescaler) -> Hpre {
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match val {
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AHBPrescaler::NotDivided => Hpre::DIV1,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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/// Configuration of the core clocks
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#[non_exhaustive]
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pub struct Config {
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pub hsi: Option<Hsi>,
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pub hse: Option<Hse>,
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pub csi: bool,
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pub hsi48: bool,
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pub sys: Sysclk,
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pub pll1: Option<Pll>,
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pub pll2: Option<Pll>,
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#[cfg(rcc_h5)]
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pub pll3: Option<Pll>,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub apb3_pre: APBPrescaler,
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pub timer_prescaler: TimerPrescaler,
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pub voltage_scale: VoltageScale,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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hsi: Some(Hsi::Mhz64),
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hse: None,
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csi: false,
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hsi48: false,
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sys: Sysclk::HSI,
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pll1: None,
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pll2: None,
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#[cfg(rcc_h5)]
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pll3: None,
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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apb3_pre: APBPrescaler::NotDivided,
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timer_prescaler: TimerPrescaler::DefaultX2,
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voltage_scale: VoltageScale::Scale3,
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}
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}
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}
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pub(crate) mod sealed {
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pub trait McoInstance {
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type Source;
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unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8);
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}
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}
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pub trait McoInstance: sealed::McoInstance + 'static {}
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pin_trait!(McoPin, McoInstance);
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macro_rules! impl_peri {
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($peri:ident, $source:ident, $set_source:ident, $set_prescaler:ident) => {
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impl sealed::McoInstance for peripherals::$peri {
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type Source = $source;
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unsafe fn apply_clock_settings(source: Self::Source, prescaler: u8) {
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RCC.cfgr().modify(|w| {
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w.$set_source(source);
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w.$set_prescaler(prescaler);
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});
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}
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}
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impl McoInstance for peripherals::$peri {}
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};
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}
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impl_peri!(MCO1, Mco1, set_mco1, set_mco1pre);
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impl_peri!(MCO2, Mco2, set_mco2, set_mco2pre);
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pub struct Mco<'d, T: McoInstance> {
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: McoInstance> Mco<'d, T> {
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pub fn new(
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_peri: impl Peripheral<P = T> + 'd,
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_pin: impl Peripheral<P = impl McoPin<T>> + 'd,
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_source: T::Source,
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) -> Self {
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todo!();
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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let (vos, max_clk) = match config.voltage_scale {
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VoltageScale::Scale0 => (Vos::SCALE0, Hertz(250_000_000)),
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VoltageScale::Scale1 => (Vos::SCALE1, Hertz(200_000_000)),
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VoltageScale::Scale2 => (Vos::SCALE2, Hertz(150_000_000)),
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VoltageScale::Scale3 => (Vos::SCALE3, Hertz(100_000_000)),
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};
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// Configure voltage scale.
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PWR.voscr().modify(|w| w.set_vos(vos));
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while !PWR.vossr().read().vosrdy() {}
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// Configure HSI
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let hsi = match config.hsi {
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None => {
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RCC.cr().modify(|w| w.set_hsion(false));
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None
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}
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Some(hsi) => {
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let (freq, hsidiv) = match hsi {
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Hsi::Mhz64 => (HSI_FREQ / 1u32, Hsidiv::DIV1),
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Hsi::Mhz32 => (HSI_FREQ / 2u32, Hsidiv::DIV2),
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Hsi::Mhz16 => (HSI_FREQ / 4u32, Hsidiv::DIV4),
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Hsi::Mhz8 => (HSI_FREQ / 8u32, Hsidiv::DIV8),
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};
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RCC.cr().modify(|w| {
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w.set_hsidiv(hsidiv);
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w.set_hsion(true);
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});
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while !RCC.cr().read().hsirdy() {}
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Some(freq)
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}
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};
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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Some(hse) => {
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let (byp, ext) = match hse.mode {
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HseMode::Oscillator => (false, Hseext::ANALOG),
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HseMode::BypassAnalog => (true, Hseext::ANALOG),
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HseMode::BypassDigital => (true, Hseext::DIGITAL),
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};
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RCC.cr().modify(|w| {
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w.set_hsebyp(byp);
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w.set_hseext(ext);
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});
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|
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RCC.cr().modify(|w| w.set_hseon(true));
|
||
|
|
while !RCC.cr().read().hserdy() {}
|
||
|
|
Some(hse.freq)
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
// Configure HSI48.
|
||
|
|
RCC.cr().modify(|w| w.set_hsi48on(config.hsi48));
|
||
|
|
let _hsi48 = match config.hsi48 {
|
||
|
|
false => None,
|
||
|
|
true => {
|
||
|
|
while !RCC.cr().read().hsi48rdy() {}
|
||
|
|
Some(CSI_FREQ)
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
// Configure CSI.
|
||
|
|
RCC.cr().modify(|w| w.set_csion(config.csi));
|
||
|
|
let csi = match config.csi {
|
||
|
|
false => None,
|
||
|
|
true => {
|
||
|
|
while !RCC.cr().read().csirdy() {}
|
||
|
|
Some(CSI_FREQ)
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
// Configure PLLs.
|
||
|
|
let pll_input = PllInput { csi, hse, hsi };
|
||
|
|
let pll1 = init_pll(0, config.pll1, &pll_input);
|
||
|
|
let _pll2 = init_pll(1, config.pll2, &pll_input);
|
||
|
|
#[cfg(rcc_h5)]
|
||
|
|
let _pll3 = init_pll(2, config.pll3, &pll_input);
|
||
|
|
|
||
|
|
// Configure sysclk
|
||
|
|
let (sys, sw) = match config.sys {
|
||
|
|
Sysclk::HSI => (unwrap!(hsi), Sw::HSI),
|
||
|
|
Sysclk::HSE => (unwrap!(hse), Sw::HSE),
|
||
|
|
Sysclk::CSI => (unwrap!(csi), Sw::CSI),
|
||
|
|
Sysclk::Pll1P => (unwrap!(pll1.p), Sw::PLL1),
|
||
|
|
};
|
||
|
|
assert!(sys <= max_clk);
|
||
|
|
|
||
|
|
let hclk = config.ahb_pre.div(sys);
|
||
|
|
|
||
|
|
let apb1 = config.apb1_pre.div(hclk);
|
||
|
|
let apb1_tim = config.apb1_pre.div_tim(hclk, config.timer_prescaler);
|
||
|
|
let apb2 = config.apb2_pre.div(hclk);
|
||
|
|
let apb2_tim = config.apb2_pre.div_tim(hclk, config.timer_prescaler);
|
||
|
|
let apb3 = config.apb3_pre.div(hclk);
|
||
|
|
|
||
|
|
flash_setup(hclk, config.voltage_scale);
|
||
|
|
|
||
|
|
// Set hpre
|
||
|
|
let hpre = config.ahb_pre.into();
|
||
|
|
RCC.cfgr2().modify(|w| w.set_hpre(hpre));
|
||
|
|
while RCC.cfgr2().read().hpre() != hpre {}
|
||
|
|
|
||
|
|
// set ppre
|
||
|
|
RCC.cfgr2().modify(|w| {
|
||
|
|
w.set_ppre1(config.apb1_pre.into());
|
||
|
|
w.set_ppre2(config.apb2_pre.into());
|
||
|
|
w.set_ppre3(config.apb3_pre.into());
|
||
|
|
});
|
||
|
|
|
||
|
|
RCC.cfgr().modify(|w| w.set_timpre(config.timer_prescaler.into()));
|
||
|
|
|
||
|
|
RCC.cfgr().modify(|w| w.set_sw(sw));
|
||
|
|
while RCC.cfgr().read().sws() != sw {}
|
||
|
|
|
||
|
|
set_freqs(Clocks {
|
||
|
|
sys,
|
||
|
|
ahb1: hclk,
|
||
|
|
ahb2: hclk,
|
||
|
|
ahb3: hclk,
|
||
|
|
ahb4: hclk,
|
||
|
|
apb1,
|
||
|
|
apb2,
|
||
|
|
apb3,
|
||
|
|
apb1_tim,
|
||
|
|
apb2_tim,
|
||
|
|
adc: None,
|
||
|
|
});
|
||
|
|
}
|
||
|
|
|
||
|
|
struct PllInput {
|
||
|
|
hsi: Option<Hertz>,
|
||
|
|
hse: Option<Hertz>,
|
||
|
|
csi: Option<Hertz>,
|
||
|
|
}
|
||
|
|
|
||
|
|
struct PllOutput {
|
||
|
|
p: Option<Hertz>,
|
||
|
|
#[allow(dead_code)]
|
||
|
|
q: Option<Hertz>,
|
||
|
|
#[allow(dead_code)]
|
||
|
|
r: Option<Hertz>,
|
||
|
|
}
|
||
|
|
|
||
|
|
unsafe fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
|
||
|
|
let Some(config) = config else {
|
||
|
|
// Stop PLL
|
||
|
|
RCC.cr().modify(|w| w.set_pllon(num, false));
|
||
|
|
while RCC.cr().read().pllrdy(num) {}
|
||
|
|
|
||
|
|
// "To save power when PLL1 is not used, the value of PLL1M must be set to 0.""
|
||
|
|
RCC.pllcfgr(num).write(|w| {
|
||
|
|
w.set_divm(0);
|
||
|
|
});
|
||
|
|
|
||
|
|
return PllOutput{
|
||
|
|
p: None,
|
||
|
|
q: None,
|
||
|
|
r: None,
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
assert!(1 <= config.prediv && config.prediv <= 63);
|
||
|
|
assert!(4 <= config.mul && config.mul <= 512);
|
||
|
|
|
||
|
|
let (in_clk, src) = match config.source {
|
||
|
|
PllSource::Hsi => (unwrap!(input.hsi), Pllsrc::HSI),
|
||
|
|
PllSource::Hse => (unwrap!(input.hse), Pllsrc::HSE),
|
||
|
|
PllSource::Csi => (unwrap!(input.csi), Pllsrc::CSI),
|
||
|
|
};
|
||
|
|
|
||
|
|
let ref_clk = in_clk / config.prediv as u32;
|
||
|
|
|
||
|
|
let ref_range = match ref_clk.0 {
|
||
|
|
..=1_999_999 => Pllrge::RANGE1,
|
||
|
|
..=3_999_999 => Pllrge::RANGE2,
|
||
|
|
..=7_999_999 => Pllrge::RANGE4,
|
||
|
|
..=16_000_000 => Pllrge::RANGE8,
|
||
|
|
x => panic!("pll ref_clk out of range: {} mhz", x),
|
||
|
|
};
|
||
|
|
|
||
|
|
// The smaller range (150 to 420 MHz) must
|
||
|
|
// be chosen when the reference clock frequency is lower than 2 MHz.
|
||
|
|
let wide_allowed = ref_range != Pllrge::RANGE1;
|
||
|
|
|
||
|
|
let vco_clk = ref_clk * config.mul;
|
||
|
|
let vco_range = match vco_clk.0 {
|
||
|
|
VCO_MIN..=VCO_MAX => Pllvcosel::MEDIUMVCO,
|
||
|
|
VCO_WIDE_MIN..=VCO_WIDE_MAX if wide_allowed => Pllvcosel::WIDEVCO,
|
||
|
|
x => panic!("pll vco_clk out of range: {} mhz", x),
|
||
|
|
};
|
||
|
|
|
||
|
|
let p = config.divp.map(|div| {
|
||
|
|
assert!(1 <= div && div <= 128);
|
||
|
|
if num == 0 {
|
||
|
|
// on PLL1, DIVP must be even.
|
||
|
|
assert!(div % 2 == 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
vco_clk / div
|
||
|
|
});
|
||
|
|
let q = config.divq.map(|div| {
|
||
|
|
assert!(1 <= div && div <= 128);
|
||
|
|
vco_clk / div
|
||
|
|
});
|
||
|
|
let r = config.divr.map(|div| {
|
||
|
|
assert!(1 <= div && div <= 128);
|
||
|
|
vco_clk / div
|
||
|
|
});
|
||
|
|
|
||
|
|
RCC.pllcfgr(num).write(|w| {
|
||
|
|
w.set_pllsrc(src);
|
||
|
|
w.set_divm(config.prediv);
|
||
|
|
w.set_pllvcosel(vco_range);
|
||
|
|
w.set_pllrge(ref_range);
|
||
|
|
w.set_pllfracen(false);
|
||
|
|
w.set_pllpen(p.is_some());
|
||
|
|
w.set_pllqen(q.is_some());
|
||
|
|
w.set_pllren(r.is_some());
|
||
|
|
});
|
||
|
|
RCC.plldivr(num).write(|w| {
|
||
|
|
w.set_plln(config.mul - 1);
|
||
|
|
w.set_pllp((config.divp.unwrap_or(1) - 1) as u8);
|
||
|
|
w.set_pllq((config.divq.unwrap_or(1) - 1) as u8);
|
||
|
|
w.set_pllr((config.divr.unwrap_or(1) - 1) as u8);
|
||
|
|
});
|
||
|
|
|
||
|
|
RCC.cr().modify(|w| w.set_pllon(num, true));
|
||
|
|
while !RCC.cr().read().pllrdy(num) {}
|
||
|
|
|
||
|
|
PllOutput { p, q, r }
|
||
|
|
}
|
||
|
|
|
||
|
|
fn flash_setup(clk: Hertz, vos: VoltageScale) {
|
||
|
|
// RM0481 Rev 1, table 37
|
||
|
|
// LATENCY WRHIGHFREQ VOS3 VOS2 VOS1 VOS0
|
||
|
|
// 0 0 0 to 20 MHz 0 to 30 MHz 0 to 34 MHz 0 to 42 MHz
|
||
|
|
// 1 0 20 to 40 MHz 30 to 60 MHz 34 to 68 MHz 42 to 84 MHz
|
||
|
|
// 2 1 40 to 60 MHz 60 to 90 MHz 68 to 102 MHz 84 to 126 MHz
|
||
|
|
// 3 1 60 to 80 MHz 90 to 120 MHz 102 to 136 MHz 126 to 168 MHz
|
||
|
|
// 4 2 80 to 100 MHz 120 to 150 MHz 136 to 170 MHz 168 to 210 MHz
|
||
|
|
// 5 2 170 to 200 MHz 210 to 250 MHz
|
||
|
|
|
||
|
|
// See RM0433 Rev 7 Table 17. FLASH recommended number of wait
|
||
|
|
// states and programming delay
|
||
|
|
let (latency, wrhighfreq) = match (vos, clk.0) {
|
||
|
|
(VoltageScale::Scale0, ..=42_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale0, ..=84_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale0, ..=126_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale0, ..=168_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale0, ..=210_000_000) => (4, 2),
|
||
|
|
(VoltageScale::Scale0, ..=250_000_000) => (5, 2),
|
||
|
|
|
||
|
|
(VoltageScale::Scale1, ..=34_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale1, ..=68_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale1, ..=102_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale1, ..=136_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale1, ..=170_000_000) => (4, 2),
|
||
|
|
(VoltageScale::Scale1, ..=200_000_000) => (5, 2),
|
||
|
|
|
||
|
|
(VoltageScale::Scale2, ..=30_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale2, ..=60_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale2, ..=90_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale2, ..=120_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale2, ..=150_000_000) => (4, 2),
|
||
|
|
|
||
|
|
(VoltageScale::Scale3, ..=20_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale3, ..=40_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale3, ..=60_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale3, ..=80_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale3, ..=100_000_000) => (4, 2),
|
||
|
|
|
||
|
|
_ => unreachable!(),
|
||
|
|
};
|
||
|
|
|
||
|
|
defmt::debug!("flash: latency={} wrhighfreq={}", latency, wrhighfreq);
|
||
|
|
|
||
|
|
// NOTE(unsafe) Atomic write
|
||
|
|
unsafe {
|
||
|
|
FLASH.acr().write(|w| {
|
||
|
|
w.set_wrhighfreq(wrhighfreq);
|
||
|
|
w.set_latency(latency);
|
||
|
|
});
|
||
|
|
while FLASH.acr().read().latency() != latency {}
|
||
|
|
}
|
||
|
|
}
|