2022-01-04 23:58:13 +01:00
|
|
|
use crate::pac::RCC;
|
|
|
|
use crate::rcc::{set_freqs, Clocks};
|
2022-07-11 00:36:10 +02:00
|
|
|
use crate::time::Hertz;
|
2021-06-14 11:41:02 +02:00
|
|
|
|
|
|
|
/// Most of clock setup is copied from stm32l0xx-hal, and adopted to the generated PAC,
|
|
|
|
/// and with the addition of the init function to configure a system clock.
|
|
|
|
|
|
|
|
/// Only the basic setup using the HSE and HSI clocks are supported as of now.
|
|
|
|
|
|
|
|
/// HSI speed
|
2022-07-10 19:59:36 +02:00
|
|
|
pub const HSI_FREQ: Hertz = Hertz(16_000_000);
|
|
|
|
|
|
|
|
/// LSI speed
|
|
|
|
pub const LSI_FREQ: Hertz = Hertz(32_000);
|
2021-06-14 11:41:02 +02:00
|
|
|
|
|
|
|
/// System clock mux source
|
|
|
|
#[derive(Clone, Copy)]
|
|
|
|
pub enum ClockSrc {
|
|
|
|
HSE(Hertz),
|
|
|
|
HSI16,
|
|
|
|
}
|
|
|
|
|
2021-11-28 16:46:08 +01:00
|
|
|
/// AHB prescaler
|
|
|
|
#[derive(Clone, Copy, PartialEq)]
|
|
|
|
pub enum AHBPrescaler {
|
|
|
|
NotDivided,
|
|
|
|
Div2,
|
|
|
|
Div3,
|
|
|
|
Div4,
|
|
|
|
Div5,
|
|
|
|
Div6,
|
|
|
|
Div8,
|
|
|
|
Div10,
|
|
|
|
Div16,
|
|
|
|
Div32,
|
|
|
|
Div64,
|
|
|
|
Div128,
|
|
|
|
Div256,
|
|
|
|
Div512,
|
|
|
|
}
|
|
|
|
|
|
|
|
/// APB prescaler
|
|
|
|
#[derive(Clone, Copy)]
|
|
|
|
pub enum APBPrescaler {
|
|
|
|
NotDivided,
|
|
|
|
Div2,
|
|
|
|
Div4,
|
|
|
|
Div8,
|
|
|
|
Div16,
|
|
|
|
}
|
|
|
|
|
2021-06-14 11:41:02 +02:00
|
|
|
impl Into<u8> for APBPrescaler {
|
|
|
|
fn into(self) -> u8 {
|
|
|
|
match self {
|
|
|
|
APBPrescaler::NotDivided => 1,
|
|
|
|
APBPrescaler::Div2 => 0x04,
|
|
|
|
APBPrescaler::Div4 => 0x05,
|
|
|
|
APBPrescaler::Div8 => 0x06,
|
|
|
|
APBPrescaler::Div16 => 0x07,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl Into<u8> for AHBPrescaler {
|
|
|
|
fn into(self) -> u8 {
|
|
|
|
match self {
|
2023-01-21 14:39:25 +01:00
|
|
|
AHBPrescaler::NotDivided => 0x0,
|
2021-06-14 11:41:02 +02:00
|
|
|
AHBPrescaler::Div2 => 0x08,
|
2021-11-28 16:46:08 +01:00
|
|
|
AHBPrescaler::Div3 => 0x01,
|
2021-06-14 11:41:02 +02:00
|
|
|
AHBPrescaler::Div4 => 0x09,
|
2021-11-28 16:46:08 +01:00
|
|
|
AHBPrescaler::Div5 => 0x02,
|
|
|
|
AHBPrescaler::Div6 => 0x05,
|
2021-06-14 11:41:02 +02:00
|
|
|
AHBPrescaler::Div8 => 0x0a,
|
2021-11-28 16:46:08 +01:00
|
|
|
AHBPrescaler::Div10 => 0x06,
|
2021-06-14 11:41:02 +02:00
|
|
|
AHBPrescaler::Div16 => 0x0b,
|
2021-11-28 16:46:08 +01:00
|
|
|
AHBPrescaler::Div32 => 0x07,
|
2021-06-14 11:41:02 +02:00
|
|
|
AHBPrescaler::Div64 => 0x0c,
|
|
|
|
AHBPrescaler::Div128 => 0x0d,
|
|
|
|
AHBPrescaler::Div256 => 0x0e,
|
|
|
|
AHBPrescaler::Div512 => 0x0f,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Clocks configutation
|
|
|
|
pub struct Config {
|
2022-01-04 11:18:59 +01:00
|
|
|
pub mux: ClockSrc,
|
|
|
|
pub ahb_pre: AHBPrescaler,
|
|
|
|
pub apb1_pre: APBPrescaler,
|
|
|
|
pub apb2_pre: APBPrescaler,
|
2021-06-14 11:41:02 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
impl Default for Config {
|
|
|
|
#[inline]
|
|
|
|
fn default() -> Config {
|
|
|
|
Config {
|
|
|
|
mux: ClockSrc::HSI16,
|
|
|
|
ahb_pre: AHBPrescaler::NotDivided,
|
|
|
|
apb1_pre: APBPrescaler::NotDivided,
|
|
|
|
apb2_pre: APBPrescaler::NotDivided,
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-01-04 23:58:13 +01:00
|
|
|
pub(crate) unsafe fn init(config: Config) {
|
|
|
|
let (sys_clk, sw) = match config.mux {
|
|
|
|
ClockSrc::HSI16 => {
|
|
|
|
// Enable HSI16
|
|
|
|
RCC.cr().write(|w| w.set_hsion(true));
|
|
|
|
while !RCC.cr().read().hsirdy() {}
|
2021-06-14 11:41:02 +02:00
|
|
|
|
2022-07-10 19:59:36 +02:00
|
|
|
(HSI_FREQ.0, 0x01)
|
2021-06-14 11:41:02 +02:00
|
|
|
}
|
2022-01-04 23:58:13 +01:00
|
|
|
ClockSrc::HSE(freq) => {
|
|
|
|
// Enable HSE
|
|
|
|
RCC.cr().write(|w| w.set_hseon(true));
|
|
|
|
while !RCC.cr().read().hserdy() {}
|
2021-06-14 11:41:02 +02:00
|
|
|
|
2022-01-04 23:58:13 +01:00
|
|
|
(freq.0, 0x02)
|
2021-06-14 11:41:02 +02:00
|
|
|
}
|
2022-01-04 23:58:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
RCC.cfgr().modify(|w| {
|
|
|
|
w.set_sw(sw.into());
|
|
|
|
w.set_hpre(config.ahb_pre.into());
|
|
|
|
w.set_ppre1(config.apb1_pre.into());
|
|
|
|
w.set_ppre2(config.apb2_pre.into());
|
|
|
|
});
|
|
|
|
|
|
|
|
let ahb_freq: u32 = match config.ahb_pre {
|
|
|
|
AHBPrescaler::NotDivided => sys_clk,
|
|
|
|
pre => {
|
|
|
|
let pre: u8 = pre.into();
|
|
|
|
let pre = 1 << (pre as u32 - 7);
|
|
|
|
sys_clk / pre
|
2021-06-14 11:41:02 +02:00
|
|
|
}
|
2022-01-04 23:58:13 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
|
|
|
|
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
|
|
|
pre => {
|
|
|
|
let pre: u8 = pre.into();
|
|
|
|
let pre: u8 = 1 << (pre - 3);
|
|
|
|
let freq = ahb_freq / pre as u32;
|
|
|
|
(freq, freq * 2)
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
|
|
|
|
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
|
|
|
pre => {
|
|
|
|
let pre: u8 = pre.into();
|
|
|
|
let pre: u8 = 1 << (pre - 3);
|
2023-03-17 04:21:39 +01:00
|
|
|
let freq = ahb_freq / pre as u32;
|
2022-01-04 23:58:13 +01:00
|
|
|
(freq, freq * 2)
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
set_freqs(Clocks {
|
2022-07-11 00:36:10 +02:00
|
|
|
sys: Hertz(sys_clk),
|
|
|
|
ahb1: Hertz(ahb_freq),
|
|
|
|
ahb2: Hertz(ahb_freq),
|
|
|
|
ahb3: Hertz(ahb_freq),
|
|
|
|
apb1: Hertz(apb1_freq),
|
|
|
|
apb2: Hertz(apb2_freq),
|
|
|
|
apb1_tim: Hertz(apb1_tim_freq),
|
|
|
|
apb2_tim: Hertz(apb2_tim_freq),
|
2022-01-04 23:58:13 +01:00
|
|
|
});
|
2021-06-14 11:41:02 +02:00
|
|
|
}
|