2021-09-05 20:03:52 +02:00
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//! FIXME discuss about which errors to print and when to panic
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2021-09-11 20:04:57 +02:00
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use std::{iter::FilterMap, path::Path, slice::Iter};
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2021-08-27 11:09:27 +02:00
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2021-11-27 02:21:53 +01:00
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const SUPPORTED_FAMILIES: &[&str] = &[
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"stm32f0",
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"stm32f1",
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2021-12-12 07:39:17 +01:00
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"stm32f3",
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2021-09-05 20:03:52 +02:00
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"stm32f4",
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"stm32f7",
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"stm32g0",
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"stm32g4",
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"stm32l0",
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"stm32l1",
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"stm32l4",
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"stm32h7",
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2021-11-02 17:03:56 +01:00
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"stm32u5",
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2021-09-05 20:03:52 +02:00
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"stm32wb55",
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"stm32wl55",
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2021-08-27 11:09:27 +02:00
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];
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const SEPARATOR_START: &str = "# BEGIN GENERATED FEATURES\n";
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const SEPARATOR_END: &str = "# END GENERATED FEATURES\n";
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const HELP: &str = "# Generated by stm32-gen-features. DO NOT EDIT.\n";
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/// True if the chip named `name` is supported else false
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fn is_supported(name: &str) -> bool {
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SUPPORTED_FAMILIES
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.iter()
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.any(|family| name.starts_with(family))
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}
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2021-09-05 20:03:52 +02:00
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type SupportedIter<'a> = FilterMap<
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Iter<'a, (String, Vec<String>)>,
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fn(&(String, Vec<String>)) -> Option<(&String, &Vec<String>)>,
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>;
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trait FilterSupported {
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fn supported(&self) -> SupportedIter;
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}
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impl FilterSupported for &[(String, Vec<String>)] {
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/// Get a new Vec with only the supported chips
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fn supported(&self) -> SupportedIter {
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self.iter()
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.filter_map(|(name, cores)| is_supported(name).then(|| (name, cores)))
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}
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}
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/// Get the list of all the chips and their supported cores
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2021-08-27 11:09:27 +02:00
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///
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/// Print errors to `stderr` when something is returned by the glob but is not in the returned
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/// [`Vec`]
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2021-09-05 20:03:52 +02:00
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///
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/// This function is slow because all the yaml files are parsed.
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pub fn chip_names_and_cores() -> Vec<(String, Vec<String>)> {
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glob::glob("../stm32-data/data/chips/*.yaml")
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.unwrap()
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.filter_map(|entry| entry.map_err(|e| eprintln!("{:?}", e)).ok())
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.filter_map(|entry| {
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if let Some(name) = entry.file_stem().and_then(|stem| stem.to_str()) {
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Some((name.to_lowercase(), chip_cores(&entry)))
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} else {
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eprintln!("{:?} is not a regular file", entry);
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None
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}
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})
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.collect()
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}
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/// Get the list of the cores of a chip by its associated file
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///
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/// # Panic
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/// Panics if the file does not exist or if it contains yaml syntax errors.
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/// Panics if "cores" is not an array.
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fn chip_cores(path: &Path) -> Vec<String> {
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let file_contents = std::fs::read_to_string(path).unwrap();
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let doc = &yaml_rust::YamlLoader::load_from_str(&file_contents).unwrap()[0];
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doc["cores"]
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.as_vec()
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.unwrap_or_else(|| panic!("{:?}:[cores] is not an array", path))
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.iter()
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.enumerate()
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.map(|(i, core)| {
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core["name"]
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.as_str()
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.unwrap_or_else(|| panic!("{:?}:[cores][{}][name] is not a string", path, i))
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.to_owned()
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})
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.collect()
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2021-08-27 11:09:27 +02:00
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}
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2021-09-05 20:03:52 +02:00
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/// Generate data needed in `../embassy-stm32/Cargo.toml`
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///
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/// Print errors to `stderr` when something is returned by the glob but is not in the returned
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/// [`Vec`]
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2021-08-27 11:09:27 +02:00
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///
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/// # Panic
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/// Panics if a file contains yaml syntax errors or if a value does not have a consistent type
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pub fn embassy_stm32_needed_data(names_and_cores: &[(String, Vec<String>)]) -> String {
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let mut result = String::new();
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for (chip_name, cores) in names_and_cores.supported() {
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2021-08-27 11:09:27 +02:00
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if cores.len() > 1 {
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for core_name in cores.iter() {
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result += &format!(
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"{chip}-{core} = [ \"stm32-metapac/{chip}-{core}\" ]\n",
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chip = chip_name,
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core = core_name
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);
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}
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} else {
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result += &format!("{chip} = [ \"stm32-metapac/{chip}\" ]\n", chip = chip_name);
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}
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}
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result
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}
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/// Generate data needed in `../stm32-metapac/Cargo.toml`
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///
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/// Print errors to `stderr` when something is returned by the glob but is not in the returned
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/// [`Vec`]
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///
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/// # Panic
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/// Panics if a file contains yaml syntax errors or if a value does not have a consistent type
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pub fn stm32_metapac_needed_data(names_and_cores: &[(String, Vec<String>)]) -> String {
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let mut result = String::new();
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for (chip_name, cores) in names_and_cores {
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if cores.len() > 1 {
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for core_name in cores {
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2021-11-23 23:49:06 +01:00
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result += &format!("{}-{} = []\n", chip_name, core_name);
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}
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} else {
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result += &format!("{} = []\n", chip_name);
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}
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}
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result
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}
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/// Get contents before and after generated contents
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///
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/// # Panic
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/// Panics when a separator cound not be not found
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fn split_cargo_toml_contents(contents: &str) -> (&str, &str) {
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let (before, remainder) = contents
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.split_once(SEPARATOR_START)
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.unwrap_or_else(|| panic!("missing \"{}\" tag", SEPARATOR_START));
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let (_, after) = remainder
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.split_once(SEPARATOR_END)
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.unwrap_or_else(|| panic!("missing \"{}\" tag", SEPARATOR_END));
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(before, after)
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}
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/// Generates new contents for Cargo.toml
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///
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/// # Panic
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/// Panics when a separator cound not be not found
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pub fn generate_cargo_toml_file(previous_text: &str, new_contents: &str) -> String {
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let (before, after) = split_cargo_toml_contents(previous_text);
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before.to_owned() + SEPARATOR_START + HELP + new_contents + SEPARATOR_END + after
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2021-08-27 11:09:27 +02:00
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}
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#[cfg(test)]
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mod tests {
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use super::*;
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#[test]
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fn stm32f407vg_is_supported() {
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assert!(is_supported("stm32f407vg"))
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}
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#[test]
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fn abcdef_is_not_supported() {
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assert!(!is_supported("abcdef"))
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}
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#[test]
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#[ignore]
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fn stm32f407vg_yaml_file_exists_and_is_supported() {
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assert!(chip_names_and_cores()
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.as_slice()
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.supported()
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.into_iter()
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.any(|(name, _)| { name == "stm32f407vg" }))
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}
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#[test]
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fn keeps_text_around_separators() {
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let initial = "\
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before
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# BEGIN GENERATED FEATURES
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# END GENERATED FEATURES
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after
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";
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let expected = "\
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before
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# BEGIN GENERATED FEATURES
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# Generated by stm32-gen-features. DO NOT EDIT.
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a = [\"b\"]
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# END GENERATED FEATURES
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after
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";
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2021-09-11 20:04:57 +02:00
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let new_contents = String::from("a = [\"b\"]\n");
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assert_eq!(generate_cargo_toml_file(initial, &new_contents), expected);
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}
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#[test]
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#[should_panic]
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fn does_not_generate_if_separators_are_missing() {
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let initial = "\
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before
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# END GENERATED FEATURES
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after
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";
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2021-09-11 20:04:57 +02:00
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let new_contents = String::from("a = [\"b\"]\n");
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generate_cargo_toml_file(initial, &new_contents);
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2021-08-27 11:09:27 +02:00
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}
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}
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