372 lines
11 KiB
Rust
372 lines
11 KiB
Rust
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use core::sync::atomic::{fence, Ordering};
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use embassy_net::{Packet, PacketBox, PacketBoxExt, PacketBuf};
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use vcell::VolatileCell;
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use crate::pac::ETH;
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#[non_exhaustive]
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#[derive(Debug, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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NoBufferAvailable,
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// TODO: Break down this error into several others
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TransmissionError,
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}
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/// Transmit and Receive Descriptor fields
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#[allow(dead_code)]
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mod emac_consts {
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pub const EMAC_DES3_OWN: u32 = 0x8000_0000;
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pub const EMAC_DES3_CTXT: u32 = 0x4000_0000;
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pub const EMAC_DES3_FD: u32 = 0x2000_0000;
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pub const EMAC_DES3_LD: u32 = 0x1000_0000;
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pub const EMAC_DES3_ES: u32 = 0x0000_8000;
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pub const EMAC_DES0_BUF1AP: u32 = 0xFFFF_FFFF;
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pub const EMAC_TDES2_IOC: u32 = 0x8000_0000;
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pub const EMAC_TDES2_B1L: u32 = 0x0000_3FFF;
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pub const EMAC_RDES3_IOC: u32 = 0x4000_0000;
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pub const EMAC_RDES3_PL: u32 = 0x0000_7FFF;
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pub const EMAC_RDES3_BUF1V: u32 = 0x0100_0000;
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pub const EMAC_RDES3_PKTLEN: u32 = 0x0000_7FFF;
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}
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use emac_consts::*;
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/// Transmit Descriptor representation
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///
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/// * tdes0: transmit buffer address
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/// * tdes1:
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/// * tdes2: buffer lengths
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/// * tdes3: control and payload/frame length
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#[repr(C)]
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struct TDes {
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tdes0: VolatileCell<u32>,
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tdes1: VolatileCell<u32>,
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tdes2: VolatileCell<u32>,
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tdes3: VolatileCell<u32>,
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}
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impl TDes {
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pub const fn new() -> Self {
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Self {
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tdes0: VolatileCell::new(0),
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tdes1: VolatileCell::new(0),
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tdes2: VolatileCell::new(0),
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tdes3: VolatileCell::new(0),
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}
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}
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/// Return true if this TDes is not currently owned by the DMA
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pub fn available(&self) -> bool {
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self.tdes3.get() & EMAC_DES3_OWN == 0
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}
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}
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pub(crate) struct TDesRing<const N: usize> {
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td: [TDes; N],
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buffers: [Option<PacketBuf>; N],
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tdidx: usize,
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}
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impl<const N: usize> TDesRing<N> {
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pub const fn new() -> Self {
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const TDES: TDes = TDes::new();
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const BUFFERS: Option<PacketBuf> = None;
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Self {
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td: [TDES; N],
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buffers: [BUFFERS; N],
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tdidx: 0,
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}
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}
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/// Initialise this TDesRing. Assume TDesRing is corrupt
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///
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/// The current memory address of the buffers inside this TDesRing
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/// will be stored in the descriptors, so ensure the TDesRing is
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/// not moved after initialisation.
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pub(crate) fn init(&mut self) {
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assert!(N > 0);
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for td in self.td.iter_mut() {
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*td = TDes::new();
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}
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self.tdidx = 0;
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// Initialize the pointers in the DMA engine. (There will be a memory barrier later
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// before the DMA engine is enabled.)
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// NOTE (unsafe) Used for atomic writes
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmactx_dlar()
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.write(|w| w.set_tdesla(&self.td as *const _ as u32));
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dma.dmactx_rlr().write(|w| w.set_tdrl((N as u16) - 1));
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dma.dmactx_dtpr()
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.write(|w| w.set_tdt(&self.td[0] as *const _ as u32));
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}
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}
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/// Return true if a TDes is available for use
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pub(crate) fn available(&self) -> bool {
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self.td[self.tdidx].available()
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}
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pub(crate) fn transmit(&mut self, pkt: PacketBuf) -> Result<(), Error> {
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if !self.available() {
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return Err(Error::NoBufferAvailable);
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}
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let x = self.tdidx;
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let td = &mut self.td[x];
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let pkt_len = pkt.len();
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assert!(pkt_len as u32 <= EMAC_TDES2_B1L);
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let address = pkt.as_ptr() as u32;
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// Read format
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td.tdes0.set(address);
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td.tdes2
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.set(pkt_len as u32 & EMAC_TDES2_B1L | EMAC_TDES2_IOC);
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// FD: Contains first buffer of packet
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// LD: Contains last buffer of packet
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// Give the DMA engine ownership
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td.tdes3.set(EMAC_DES3_FD | EMAC_DES3_LD | EMAC_DES3_OWN);
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self.buffers[x].replace(pkt);
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// Ensure changes to the descriptor are committed before DMA engine sees tail pointer store.
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// This will generate an DMB instruction.
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::Release);
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// Move the tail pointer (TPR) to the next descriptor
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let x = (x + 1) % N;
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// NOTE(unsafe) Atomic write
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unsafe {
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ETH.ethernet_dma()
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.dmactx_dtpr()
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.write(|w| w.set_tdt(&self.td[x] as *const _ as u32));
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}
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self.tdidx = x;
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Ok(())
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}
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pub(crate) fn on_interrupt(&mut self) -> Result<(), Error> {
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let previous = (self.tdidx + N - 1) % N;
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let td = &self.td[previous];
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// DMB to ensure that we are reading an updated value, probably not needed at the hardware
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// level, but this is also a hint to the compiler that we're syncing on the buffer.
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fence(Ordering::SeqCst);
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let tdes3 = td.tdes3.get();
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if tdes3 & EMAC_DES3_OWN != 0 {
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// Transmission isn't done yet, probably a receive interrupt that fired this
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return Ok(());
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}
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assert!(tdes3 & EMAC_DES3_CTXT == 0);
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// Release the buffer
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self.buffers[previous].take();
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if tdes3 & EMAC_DES3_ES != 0 {
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Err(Error::TransmissionError)
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} else {
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Ok(())
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}
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}
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}
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/// Receive Descriptor representation
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///
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/// * rdes0: recieve buffer address
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/// * rdes1:
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/// * rdes2:
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/// * rdes3: OWN and Status
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#[repr(C)]
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struct RDes {
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rdes0: VolatileCell<u32>,
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rdes1: VolatileCell<u32>,
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rdes2: VolatileCell<u32>,
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rdes3: VolatileCell<u32>,
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}
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impl RDes {
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pub const fn new() -> Self {
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Self {
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rdes0: VolatileCell::new(0),
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rdes1: VolatileCell::new(0),
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rdes2: VolatileCell::new(0),
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rdes3: VolatileCell::new(0),
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}
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}
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/// Return true if this RDes is acceptable to us
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#[inline(always)]
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pub fn valid(&self) -> bool {
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// Write-back descriptor is valid if:
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//
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// Contains first buffer of packet AND contains last buf of
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// packet AND no errors AND not a context descriptor
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self.rdes3.get() & (EMAC_DES3_FD | EMAC_DES3_LD | EMAC_DES3_ES | EMAC_DES3_CTXT)
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== (EMAC_DES3_FD | EMAC_DES3_LD)
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}
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/// Return true if this RDes is not currently owned by the DMA
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#[inline(always)]
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pub fn available(&self) -> bool {
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self.rdes3.get() & EMAC_DES3_OWN == 0 // Owned by us
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}
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#[inline(always)]
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pub fn set_ready(&mut self, buf_addr: u32) {
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self.rdes0.set(buf_addr);
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self.rdes3
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.set(EMAC_RDES3_BUF1V | EMAC_RDES3_IOC | EMAC_DES3_OWN);
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}
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}
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pub(crate) struct RDesRing<const N: usize> {
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rd: [RDes; N],
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buffers: [Option<PacketBox>; N],
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read_idx: usize,
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tail_idx: usize,
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}
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impl<const N: usize> RDesRing<N> {
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pub const fn new() -> Self {
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const RDES: RDes = RDes::new();
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const BUFFERS: Option<PacketBox> = None;
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Self {
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rd: [RDES; N],
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buffers: [BUFFERS; N],
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read_idx: 0,
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tail_idx: 0,
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}
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}
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pub(crate) fn init(&mut self) {
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assert!(N > 1);
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for desc in self.rd.iter_mut() {
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*desc = RDes::new();
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}
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let mut last_index = 0;
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for (index, buf) in self.buffers.iter_mut().enumerate() {
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let pkt = match PacketBox::new(Packet::new()) {
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Some(p) => p,
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None => {
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if index == 0 {
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panic!("Could not allocate at least one buffer for Ethernet receiving");
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} else {
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break;
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}
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}
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};
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let addr = pkt.as_ptr() as u32;
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*buf = Some(pkt);
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self.rd[index].set_ready(addr);
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last_index = index;
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}
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self.tail_idx = (last_index + 1) % N;
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmacrx_dlar()
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.write(|w| w.set_rdesla(self.rd.as_ptr() as u32));
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dma.dmacrx_rlr().write(|w| w.set_rdrl((N as u16) - 1));
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// We manage to allocate all buffers, set the index to the last one, that means
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// that the DMA won't consider the last one as ready, because it (unfortunately)
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// stops at the tail ptr and wraps at the end of the ring, which means that we
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// can't tell it to stop after the last buffer.
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let tail_ptr = &self.rd[last_index] as *const _ as u32;
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fence(Ordering::Release);
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dma.dmacrx_dtpr().write(|w| w.set_rdt(tail_ptr));
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}
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}
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pub(crate) fn on_interrupt(&mut self) {
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// TODO!
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}
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pub(crate) fn pop_packet(&mut self) -> Option<PacketBuf> {
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// Not sure if the contents of the write buffer on the M7 can affects reads, so we are using
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// a DMB here just in case, it also serves as a hint to the compiler that we're syncing the
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// buffer (I think .-.)
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fence(Ordering::SeqCst);
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let read_available = self.rd[self.read_idx].available();
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if !read_available && self.read_idx == self.tail_idx {
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// Nothing to do
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return None;
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}
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let pkt = if read_available {
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let pkt = self.buffers[self.read_idx].take();
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let len = (self.rd[self.read_idx].rdes3.get() & EMAC_RDES3_PKTLEN) as usize;
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assert!(pkt.is_some());
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let valid = self.rd[self.read_idx].valid();
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self.read_idx = (self.read_idx + 1) % N;
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if valid {
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pkt.map(|p| p.slice(0..len))
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} else {
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None
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}
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} else {
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None
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};
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match PacketBox::new(Packet::new()) {
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Some(b) => {
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let addr = b.as_ptr() as u32;
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self.buffers[self.tail_idx].replace(b);
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self.rd[self.tail_idx].set_ready(addr);
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::Release);
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// NOTE(unsafe) atomic write
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unsafe {
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ETH.ethernet_dma()
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.dmacrx_dtpr()
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.write(|w| w.set_rdt(&self.rd[self.read_idx] as *const _ as u32));
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}
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self.tail_idx = (self.tail_idx + 1) % N;
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}
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None => {}
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}
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pkt
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}
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}
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pub struct DescriptorRing<const T: usize, const R: usize> {
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pub(crate) tx: TDesRing<T>,
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pub(crate) rx: RDesRing<R>,
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}
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impl<const T: usize, const R: usize> DescriptorRing<T, R> {
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pub const fn new() -> Self {
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Self {
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tx: TDesRing::new(),
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rx: RDesRing::new(),
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}
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}
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pub fn init(&mut self) {
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self.tx.init();
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self.rx.init();
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}
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}
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