2021-03-29 04:11:32 +02:00
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use core::marker::PhantomData;
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2021-04-14 19:59:52 +02:00
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use embassy::util::Unborrow;
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2021-07-29 13:44:51 +02:00
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use embassy_hal_common::unborrow;
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2021-03-29 04:11:32 +02:00
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use gpio::Pin;
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use crate::{gpio, pac, peripherals};
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#[non_exhaustive]
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pub struct Config {
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pub baudrate: u32,
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pub data_bits: u8,
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pub stop_bits: u8,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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baudrate: 115200,
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data_bits: 8,
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stop_bits: 1,
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}
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}
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}
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pub struct Uart<'d, T: Instance> {
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inner: T,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Uart<'d, T> {
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pub fn new(
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2021-04-14 19:59:52 +02:00
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inner: impl Unborrow<Target = T>,
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tx: impl Unborrow<Target = impl TxPin<T>>,
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rx: impl Unborrow<Target = impl RxPin<T>>,
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cts: impl Unborrow<Target = impl CtsPin<T>>,
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rts: impl Unborrow<Target = impl RtsPin<T>>,
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2021-03-29 04:11:32 +02:00
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config: Config,
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) -> Self {
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unborrow!(inner, tx, rx, cts, rts);
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unsafe {
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let p = inner.regs();
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2021-06-25 03:38:03 +02:00
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let clk_base = crate::clocks::clk_peri_freq();
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2021-03-29 04:11:32 +02:00
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let baud_rate_div = (8 * clk_base) / config.baudrate;
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let mut baud_ibrd = baud_rate_div >> 7;
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let mut baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
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if baud_ibrd == 0 {
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baud_ibrd = 1;
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baud_fbrd = 0;
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} else if baud_ibrd >= 65535 {
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baud_ibrd = 65535;
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baud_fbrd = 0;
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}
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// Load PL011's baud divisor registers
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p.uartibrd()
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.write_value(pac::uart::regs::Uartibrd(baud_ibrd));
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p.uartfbrd()
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.write_value(pac::uart::regs::Uartfbrd(baud_fbrd));
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p.uartlcr_h().write(|w| {
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w.set_wlen(config.data_bits - 5);
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w.set_stp2(config.stop_bits == 2);
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w.set_pen(false);
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w.set_eps(false);
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w.set_fen(true);
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});
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p.uartcr().write(|w| {
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w.set_uarten(true);
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w.set_rxe(true);
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w.set_txe(true);
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});
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tx.io().ctrl().write(|w| w.set_funcsel(2));
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rx.io().ctrl().write(|w| w.set_funcsel(2));
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cts.io().ctrl().write(|w| w.set_funcsel(2));
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rts.io().ctrl().write(|w| w.set_funcsel(2));
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}
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Self {
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inner,
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phantom: PhantomData,
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}
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}
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pub fn send(&mut self, data: &[u8]) {
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unsafe {
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let p = self.inner.regs();
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for &byte in data {
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if !p.uartfr().read().txff() {
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p.uartdr().write(|w| w.set_data(byte));
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}
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}
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}
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}
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}
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mod sealed {
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use super::*;
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pub trait Instance {
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fn regs(&self) -> pac::uart::Uart;
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}
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pub trait TxPin<T: Instance> {}
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pub trait RxPin<T: Instance> {}
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pub trait CtsPin<T: Instance> {}
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pub trait RtsPin<T: Instance> {}
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}
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pub trait Instance: sealed::Instance {}
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macro_rules! impl_instance {
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($type:ident, $irq:ident) => {
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impl sealed::Instance for peripherals::$type {
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fn regs(&self) -> pac::uart::Uart {
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pac::$type
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}
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}
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impl Instance for peripherals::$type {}
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};
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}
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impl_instance!(UART0, UART0);
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impl_instance!(UART1, UART1);
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pub trait TxPin<T: Instance>: sealed::TxPin<T> + Pin {}
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pub trait RxPin<T: Instance>: sealed::RxPin<T> + Pin {}
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pub trait CtsPin<T: Instance>: sealed::CtsPin<T> + Pin {}
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pub trait RtsPin<T: Instance>: sealed::RtsPin<T> + Pin {}
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macro_rules! impl_pin {
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($pin:ident, $instance:ident, $function:ident) => {
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impl sealed::$function<peripherals::$instance> for peripherals::$pin {}
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impl $function<peripherals::$instance> for peripherals::$pin {}
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};
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}
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impl_pin!(PIN_0, UART0, TxPin);
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impl_pin!(PIN_1, UART0, RxPin);
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impl_pin!(PIN_2, UART0, CtsPin);
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impl_pin!(PIN_3, UART0, RtsPin);
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impl_pin!(PIN_4, UART1, TxPin);
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impl_pin!(PIN_5, UART1, RxPin);
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impl_pin!(PIN_6, UART1, CtsPin);
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impl_pin!(PIN_7, UART1, RtsPin);
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impl_pin!(PIN_8, UART1, TxPin);
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impl_pin!(PIN_9, UART1, RxPin);
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impl_pin!(PIN_10, UART1, CtsPin);
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impl_pin!(PIN_11, UART1, RtsPin);
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impl_pin!(PIN_12, UART0, TxPin);
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impl_pin!(PIN_13, UART0, RxPin);
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impl_pin!(PIN_14, UART0, CtsPin);
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impl_pin!(PIN_15, UART0, RtsPin);
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impl_pin!(PIN_16, UART0, TxPin);
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impl_pin!(PIN_17, UART0, RxPin);
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impl_pin!(PIN_18, UART0, CtsPin);
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impl_pin!(PIN_19, UART0, RtsPin);
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impl_pin!(PIN_20, UART1, TxPin);
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impl_pin!(PIN_21, UART1, RxPin);
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impl_pin!(PIN_22, UART1, CtsPin);
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impl_pin!(PIN_23, UART1, RtsPin);
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impl_pin!(PIN_24, UART1, TxPin);
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impl_pin!(PIN_25, UART1, RxPin);
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impl_pin!(PIN_26, UART1, CtsPin);
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impl_pin!(PIN_27, UART1, RtsPin);
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impl_pin!(PIN_28, UART0, TxPin);
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impl_pin!(PIN_29, UART0, RxPin);
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