310 lines
10 KiB
Rust
310 lines
10 KiB
Rust
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use core::sync::atomic::{compiler_fence, fence, Ordering};
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use embassy_net::{Packet, PacketBox, PacketBoxExt, PacketBuf};
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use stm32_metapac::eth::vals::{DmaomrSr, Rpd, Rps};
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use vcell::VolatileCell;
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use crate::pac::ETH;
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mod rx_consts {
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/// Owned by DMA engine
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pub const RXDESC_0_OWN: u32 = 1 << 31;
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/// First descriptor
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pub const RXDESC_0_FS: u32 = 1 << 9;
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/// Last descriptor
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pub const RXDESC_0_LS: u32 = 1 << 8;
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/// Error summary
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pub const RXDESC_0_ES: u32 = 1 << 15;
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/// Frame length
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pub const RXDESC_0_FL_MASK: u32 = 0x3FFF;
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pub const RXDESC_0_FL_SHIFT: usize = 16;
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pub const RXDESC_1_RBS_MASK: u32 = 0x0fff;
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/// Second address chained
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pub const RXDESC_1_RCH: u32 = 1 << 14;
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/// End Of Ring
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pub const RXDESC_1_RER: u32 = 1 << 15;
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}
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use rx_consts::*;
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/// Receive Descriptor representation
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///
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/// * rdes0: OWN and Status
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/// * rdes1: allocated buffer length
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/// * rdes2: data buffer address
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/// * rdes3: next descriptor address
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#[repr(C)]
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struct RDes {
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rdes0: VolatileCell<u32>,
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rdes1: VolatileCell<u32>,
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rdes2: VolatileCell<u32>,
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rdes3: VolatileCell<u32>,
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}
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impl RDes {
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pub const fn new() -> Self {
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Self {
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rdes0: VolatileCell::new(0),
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rdes1: VolatileCell::new(0),
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rdes2: VolatileCell::new(0),
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rdes3: VolatileCell::new(0),
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}
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}
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/// Return true if this RDes is acceptable to us
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#[inline(always)]
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pub fn valid(&self) -> bool {
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// Write-back descriptor is valid if:
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//
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// Contains first buffer of packet AND contains last buf of
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// packet AND no errors
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(self.rdes0.get() & (RXDESC_0_ES | RXDESC_0_FS | RXDESC_0_LS))
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== (RXDESC_0_FS | RXDESC_0_LS)
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}
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/// Return true if this RDes is not currently owned by the DMA
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#[inline(always)]
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pub fn available(&self) -> bool {
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self.rdes0.get() & RXDESC_0_OWN == 0 // Owned by us
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}
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/// Configures the reception buffer address and length and passed descriptor ownership to the DMA
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#[inline(always)]
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pub fn set_ready(&mut self, buf_addr: u32, buf_len: usize) {
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self.rdes1
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.set(self.rdes1.get() | (buf_len as u32) & RXDESC_1_RBS_MASK);
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self.rdes2.set(buf_addr);
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::Release);
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compiler_fence(Ordering::Release);
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self.rdes0.set(self.rdes0.get() | RXDESC_0_OWN);
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// Used to flush the store buffer as fast as possible to make the buffer available for the
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// DMA.
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fence(Ordering::SeqCst);
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}
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// points to next descriptor (RCH)
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#[inline(always)]
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fn set_buffer2(&mut self, buffer: *const u8) {
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self.rdes3.set(buffer as u32);
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}
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#[inline(always)]
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fn set_end_of_ring(&mut self) {
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self.rdes1.set(self.rdes1.get() | RXDESC_1_RER);
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}
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#[inline(always)]
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fn packet_len(&self) -> usize {
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((self.rdes0.get() >> RXDESC_0_FL_SHIFT) & RXDESC_0_FL_MASK) as usize
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}
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pub fn setup(&mut self, next: Option<&Self>) {
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// Defer this initialization to this function, so we can have `RingEntry` on bss.
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self.rdes1.set(self.rdes1.get() | RXDESC_1_RCH);
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match next {
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Some(next) => self.set_buffer2(next as *const _ as *const u8),
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None => {
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self.set_buffer2(0 as *const u8);
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self.set_end_of_ring();
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}
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}
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}
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}
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/// Running state of the `RxRing`
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#[derive(PartialEq, Eq, Debug)]
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pub enum RunningState {
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Unknown,
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Stopped,
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Running,
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}
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impl RunningState {
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/// whether self equals to `RunningState::Running`
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pub fn is_running(&self) -> bool {
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*self == RunningState::Running
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}
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}
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/// Rx ring of descriptors and packets
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///
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/// This ring has three major locations that work in lock-step. The DMA will never write to the tail
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/// index, so the `read_index` must never pass the tail index. The `next_tail_index` is always 1
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/// slot ahead of the real tail index, and it must never pass the `read_index` or it could overwrite
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/// a packet still to be passed to the application.
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///
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/// nt can't pass r (no alloc)
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/// +---+---+---+---+ Read ok +---+---+---+---+ No Read +---+---+---+---+
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/// | | | | | ------------> | | | | | ------------> | | | | |
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/// +---+---+---+---+ Allocation ok +---+---+---+---+ +---+---+---+---+
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/// ^ ^t ^t ^ ^t ^
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/// |r |r |r
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/// |nt |nt |nt
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///
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///
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/// +---+---+---+---+ Read ok +---+---+---+---+ Can't read +---+---+---+---+
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/// | | | | | ------------> | | | | | ------------> | | | | |
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/// +---+---+---+---+ Allocation fail +---+---+---+---+ Allocation ok +---+---+---+---+
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/// ^ ^t ^ ^t ^ ^ ^ ^t
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/// |r | |r | | |r
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/// |nt |nt |nt
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///
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pub(crate) struct RDesRing<const N: usize> {
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descriptors: [RDes; N],
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buffers: [Option<PacketBox>; N],
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read_index: usize,
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next_tail_index: usize,
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}
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impl<const N: usize> RDesRing<N> {
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pub const fn new() -> Self {
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const RDES: RDes = RDes::new();
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const BUFFERS: Option<PacketBox> = None;
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Self {
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descriptors: [RDES; N],
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buffers: [BUFFERS; N],
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read_index: 0,
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next_tail_index: 0,
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}
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}
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pub(crate) fn init(&mut self) {
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assert!(N > 1);
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let mut last_index = 0;
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for (index, buf) in self.buffers.iter_mut().enumerate() {
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let pkt = match PacketBox::new(Packet::new()) {
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Some(p) => p,
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None => {
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if index == 0 {
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panic!("Could not allocate at least one buffer for Ethernet receiving");
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} else {
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break;
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}
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}
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};
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self.descriptors[index].set_ready(pkt.as_ptr() as u32, pkt.len());
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*buf = Some(pkt);
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last_index = index;
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}
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self.next_tail_index = (last_index + 1) % N;
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// not sure if this is supposed to span all of the descriptor or just those that contain buffers
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{
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let mut previous: Option<&mut RDes> = None;
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for entry in self.descriptors.iter_mut() {
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if let Some(prev) = &mut previous {
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prev.setup(Some(entry));
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}
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previous = Some(entry);
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}
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if let Some(entry) = &mut previous {
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entry.setup(None);
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}
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}
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// Register txdescriptor start
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// NOTE (unsafe) Used for atomic writes
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unsafe {
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ETH.ethernet_dma()
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.dmardlar()
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.write(|w| w.0 = &self.descriptors as *const _ as u32);
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};
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// We already have fences in `set_owned`, which is called in `setup`
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// Start receive
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unsafe {
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ETH.ethernet_dma()
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.dmaomr()
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.modify(|w| w.set_sr(DmaomrSr::STARTED))
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};
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self.demand_poll();
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}
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fn demand_poll(&self) {
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unsafe { ETH.ethernet_dma().dmarpdr().write(|w| w.set_rpd(Rpd::POLL)) };
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}
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pub(crate) fn on_interrupt(&mut self) {
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// XXX: Do we need to do anything here ? Maybe we should try to advance the tail ptr, but it
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// would soon hit the read ptr anyway, and we will wake smoltcp's stack on the interrupt
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// which should try to pop a packet...
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}
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/// Get current `RunningState`
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fn running_state(&self) -> RunningState {
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match unsafe { ETH.ethernet_dma().dmasr().read().rps() } {
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// Reset or Stop Receive Command issued
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Rps::STOPPED => RunningState::Stopped,
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// Fetching receive transfer descriptor
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Rps::RUNNINGFETCHING => RunningState::Running,
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// Waiting for receive packet
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Rps::RUNNINGWAITING => RunningState::Running,
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// Receive descriptor unavailable
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Rps::SUSPENDED => RunningState::Stopped,
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// Closing receive descriptor
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Rps(0b101) => RunningState::Running,
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// Transferring the receive packet data from receive buffer to host memory
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Rps::RUNNINGWRITING => RunningState::Running,
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_ => RunningState::Unknown,
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}
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}
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pub(crate) fn pop_packet(&mut self) -> Option<PacketBuf> {
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if !self.running_state().is_running() {
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self.demand_poll();
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}
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// Not sure if the contents of the write buffer on the M7 can affects reads, so we are using
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// a DMB here just in case, it also serves as a hint to the compiler that we're syncing the
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// buffer (I think .-.)
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fence(Ordering::SeqCst);
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let read_available = self.descriptors[self.read_index].available();
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let tail_index = (self.next_tail_index + N - 1) % N;
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let pkt = if read_available && self.read_index != tail_index {
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let pkt = self.buffers[self.read_index].take();
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let len = self.descriptors[self.read_index].packet_len();
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assert!(pkt.is_some());
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let valid = self.descriptors[self.read_index].valid();
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self.read_index = (self.read_index + 1) % N;
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if valid {
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pkt.map(|p| p.slice(0..len))
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} else {
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None
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}
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} else {
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None
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};
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// Try to advance the tail_index
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if self.next_tail_index != self.read_index {
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match PacketBox::new(Packet::new()) {
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Some(b) => {
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let addr = b.as_ptr() as u32;
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let buffer_len = b.len();
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self.buffers[self.next_tail_index].replace(b);
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self.descriptors[self.next_tail_index].set_ready(addr, buffer_len);
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::Release);
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self.next_tail_index = (self.next_tail_index + 1) % N;
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}
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None => {}
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}
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}
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pkt
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}
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}
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