773 lines
25 KiB
Rust
773 lines
25 KiB
Rust
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use core::ops::RangeInclusive;
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use crate::pac;
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use crate::pac::pwr::vals::Vos;
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#[cfg(stm32h5)]
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pub use crate::pac::rcc::vals::Adcdacsel as AdcClockSource;
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#[cfg(stm32h7)]
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pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
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pub use crate::pac::rcc::vals::Ckpersel as PerClockSource;
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use crate::pac::rcc::vals::{Ckpersel, Hsidiv, Pllrge, Pllsrc, Pllvcosel, Sw, Timpre};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(64_000_000);
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/// CSI speed
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pub const CSI_FREQ: Hertz = Hertz(4_000_000);
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/// HSI48 speed
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pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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const VCO_RANGE: RangeInclusive<u32> = 150_000_000..=420_000_000;
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#[cfg(any(stm32h5, pwr_h7rm0455))]
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const VCO_WIDE_RANGE: RangeInclusive<u32> = 128_000_000..=560_000_000;
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#[cfg(pwr_h7rm0468)]
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const VCO_WIDE_RANGE: RangeInclusive<u32> = 192_000_000..=836_000_000;
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#[cfg(any(pwr_h7rm0399, pwr_h7rm0433))]
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const VCO_WIDE_RANGE: RangeInclusive<u32> = 192_000_000..=960_000_000;
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pub use super::bus::{AHBPrescaler, APBPrescaler};
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum VoltageScale {
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Scale0,
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Scale1,
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Scale2,
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Scale3,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum HseMode {
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/// crystal/ceramic oscillator (HSEBYP=0)
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Oscillator,
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/// external analog clock (low swing) (HSEBYP=1, HSEEXT=0)
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Bypass,
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/// external digital clock (full swing) (HSEBYP=1, HSEEXT=1)
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#[cfg(any(rcc_h5, rcc_h50))]
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BypassDigital,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub struct Hse {
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/// HSE frequency.
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pub freq: Hertz,
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/// HSE mode.
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pub mode: HseMode,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum Hsi {
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/// 64Mhz
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Mhz64,
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/// 32Mhz (divided by 2)
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Mhz32,
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/// 16Mhz (divided by 4)
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Mhz16,
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/// 8Mhz (divided by 8)
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Mhz8,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum Sysclk {
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/// HSI selected as sysclk
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HSI,
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/// HSE selected as sysclk
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HSE,
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/// CSI selected as sysclk
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CSI,
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/// PLL1_P selected as sysclk
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Pll1P,
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}
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum PllSource {
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Hsi,
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Csi,
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Hse,
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}
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// Source clock selection.
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#[cfg(stm32h5)]
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pub source: PllSource,
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/// PLL pre-divider (DIVM). Must be between 1 and 63.
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pub prediv: u8,
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/// PLL multiplication factor. Must be between 4 and 512.
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pub mul: u16,
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/// PLL P division factor. If None, PLL P output is disabled. Must be between 1 and 128.
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/// On PLL1, it must be even (in particular, it cannot be 1.)
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pub divp: Option<u16>,
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/// PLL Q division factor. If None, PLL Q output is disabled. Must be between 1 and 128.
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pub divq: Option<u16>,
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/// PLL R division factor. If None, PLL R output is disabled. Must be between 1 and 128.
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pub divr: Option<u16>,
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}
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fn apb_div_tim(apb: &APBPrescaler, clk: Hertz, tim: TimerPrescaler) -> Hertz {
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match (tim, apb) {
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(TimerPrescaler::DefaultX2, APBPrescaler::DIV1) => clk,
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(TimerPrescaler::DefaultX2, APBPrescaler::DIV2) => clk,
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(TimerPrescaler::DefaultX2, APBPrescaler::DIV4) => clk / 2u32,
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(TimerPrescaler::DefaultX2, APBPrescaler::DIV8) => clk / 4u32,
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(TimerPrescaler::DefaultX2, APBPrescaler::DIV16) => clk / 8u32,
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(TimerPrescaler::DefaultX4, APBPrescaler::DIV1) => clk,
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(TimerPrescaler::DefaultX4, APBPrescaler::DIV2) => clk,
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(TimerPrescaler::DefaultX4, APBPrescaler::DIV4) => clk,
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(TimerPrescaler::DefaultX4, APBPrescaler::DIV8) => clk / 2u32,
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(TimerPrescaler::DefaultX4, APBPrescaler::DIV16) => clk / 4u32,
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_ => unreachable!(),
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}
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}
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/// Timer prescaler
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#[derive(Clone, Copy, Eq, PartialEq)]
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pub enum TimerPrescaler {
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/// The timers kernel clock is equal to hclk if PPREx corresponds to a
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/// division by 1 or 2, else it is equal to 2*pclk
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DefaultX2,
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/// The timers kernel clock is equal to hclk if PPREx corresponds to a
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/// division by 1, 2 or 4, else it is equal to 4*pclk
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DefaultX4,
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}
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impl From<TimerPrescaler> for Timpre {
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fn from(value: TimerPrescaler) -> Self {
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match value {
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TimerPrescaler::DefaultX2 => Timpre::DEFAULTX2,
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TimerPrescaler::DefaultX4 => Timpre::DEFAULTX4,
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}
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}
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}
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/// Configuration of the core clocks
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#[non_exhaustive]
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pub struct Config {
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pub hsi: Option<Hsi>,
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pub hse: Option<Hse>,
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pub csi: bool,
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pub hsi48: bool,
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pub sys: Sysclk,
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#[cfg(stm32h7)]
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pub pll_src: PllSource,
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pub pll1: Option<Pll>,
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pub pll2: Option<Pll>,
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#[cfg(any(rcc_h5, stm32h7))]
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pub pll3: Option<Pll>,
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pub d1c_pre: AHBPrescaler,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub apb3_pre: APBPrescaler,
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#[cfg(stm32h7)]
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pub apb4_pre: APBPrescaler,
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pub per_clock_source: PerClockSource,
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pub adc_clock_source: AdcClockSource,
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pub timer_prescaler: TimerPrescaler,
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pub voltage_scale: VoltageScale,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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hsi: Some(Hsi::Mhz64),
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hse: None,
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csi: false,
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hsi48: false,
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sys: Sysclk::HSI,
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#[cfg(stm32h7)]
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pll_src: PllSource::Hsi,
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pll1: None,
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pll2: None,
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#[cfg(any(rcc_h5, stm32h7))]
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pll3: None,
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d1c_pre: AHBPrescaler::DIV1,
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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apb3_pre: APBPrescaler::DIV1,
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#[cfg(stm32h7)]
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apb4_pre: APBPrescaler::DIV1,
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per_clock_source: PerClockSource::HSI,
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adc_clock_source: AdcClockSource::from_bits(0), // PLL2_P on H7, HCLK on H5
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timer_prescaler: TimerPrescaler::DefaultX2,
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voltage_scale: VoltageScale::Scale0,
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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// NB. The lower bytes of CR3 can only be written once after
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// POR, and must be written with a valid combination. Refer to
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// RM0433 Rev 7 6.8.4. This is partially enforced by dropping
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// `self` at the end of this method, but of course we cannot
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// know what happened between the previous POR and here.
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#[cfg(pwr_h7rm0433)]
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PWR.cr3().modify(|w| {
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w.set_scuen(true);
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w.set_ldoen(true);
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w.set_bypass(false);
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});
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#[cfg(any(pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
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PWR.cr3().modify(|w| {
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// hardcode "Direct SPMS" for now, this is what works on nucleos with the
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// default solderbridge configuration.
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w.set_sden(true);
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w.set_ldoen(false);
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});
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// Validate the supply configuration. If you are stuck here, it is
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// because the voltages on your board do not match those specified
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// in the D3CR.VOS and CR3.SDLEVEL fields. By default after reset
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// VOS = Scale 3, so check that the voltage on the VCAP pins =
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// 1.0V.
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#[cfg(any(pwr_h7rm0433, pwr_h7rm0399, pwr_h7rm0455, pwr_h7rm0468))]
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while !PWR.csr1().read().actvosrdy() {}
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// Configure voltage scale.
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#[cfg(any(pwr_h5, pwr_h50))]
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{
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PWR.voscr().modify(|w| {
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w.set_vos(match config.voltage_scale {
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VoltageScale::Scale0 => Vos::SCALE0,
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VoltageScale::Scale1 => Vos::SCALE1,
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VoltageScale::Scale2 => Vos::SCALE2,
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VoltageScale::Scale3 => Vos::SCALE3,
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})
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});
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while !PWR.vossr().read().vosrdy() {}
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}
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#[cfg(syscfg_h7)]
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{
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// in chips without the overdrive bit, we can go from any scale to any scale directly.
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PWR.d3cr().modify(|w| {
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w.set_vos(match config.voltage_scale {
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VoltageScale::Scale0 => Vos::SCALE0,
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VoltageScale::Scale1 => Vos::SCALE1,
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VoltageScale::Scale2 => Vos::SCALE2,
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VoltageScale::Scale3 => Vos::SCALE3,
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})
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});
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while !PWR.d3cr().read().vosrdy() {}
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}
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#[cfg(syscfg_h7od)]
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{
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match config.voltage_scale {
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VoltageScale::Scale0 => {
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// to go to scale0, we must go to Scale1 first...
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PWR.d3cr().modify(|w| w.set_vos(Vos::SCALE1));
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while !PWR.d3cr().read().vosrdy() {}
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// Then enable overdrive.
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critical_section::with(|_| pac::SYSCFG.pwrcr().modify(|w| w.set_oden(1)));
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while !PWR.d3cr().read().vosrdy() {}
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}
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_ => {
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// for all other scales, we can go directly.
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PWR.d3cr().modify(|w| {
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w.set_vos(match config.voltage_scale {
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VoltageScale::Scale0 => unreachable!(),
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VoltageScale::Scale1 => Vos::SCALE1,
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VoltageScale::Scale2 => Vos::SCALE2,
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VoltageScale::Scale3 => Vos::SCALE3,
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})
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});
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while !PWR.d3cr().read().vosrdy() {}
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}
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}
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}
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// Configure HSI
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let hsi = match config.hsi {
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None => {
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RCC.cr().modify(|w| w.set_hsion(false));
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None
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}
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Some(hsi) => {
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let (freq, hsidiv) = match hsi {
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Hsi::Mhz64 => (HSI_FREQ / 1u32, Hsidiv::DIV1),
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Hsi::Mhz32 => (HSI_FREQ / 2u32, Hsidiv::DIV2),
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Hsi::Mhz16 => (HSI_FREQ / 4u32, Hsidiv::DIV4),
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Hsi::Mhz8 => (HSI_FREQ / 8u32, Hsidiv::DIV8),
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};
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RCC.cr().modify(|w| {
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w.set_hsidiv(hsidiv);
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w.set_hsion(true);
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});
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while !RCC.cr().read().hsirdy() {}
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Some(freq)
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}
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};
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// Configure HSE
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let hse = match config.hse {
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None => {
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RCC.cr().modify(|w| w.set_hseon(false));
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None
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}
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Some(hse) => {
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RCC.cr().modify(|w| {
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w.set_hsebyp(hse.mode != HseMode::Oscillator);
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#[cfg(any(rcc_h5, rcc_h50))]
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w.set_hseext(match hse.mode {
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HseMode::Oscillator | HseMode::Bypass => pac::rcc::vals::Hseext::ANALOG,
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HseMode::BypassDigital => pac::rcc::vals::Hseext::DIGITAL,
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});
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});
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RCC.cr().modify(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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Some(hse.freq)
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}
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};
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// Configure HSI48.
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RCC.cr().modify(|w| w.set_hsi48on(config.hsi48));
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let _hsi48 = match config.hsi48 {
|
||
|
|
false => None,
|
||
|
|
true => {
|
||
|
|
while !RCC.cr().read().hsi48rdy() {}
|
||
|
|
Some(CSI_FREQ)
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
// Configure CSI.
|
||
|
|
RCC.cr().modify(|w| w.set_csion(config.csi));
|
||
|
|
let csi = match config.csi {
|
||
|
|
false => None,
|
||
|
|
true => {
|
||
|
|
while !RCC.cr().read().csirdy() {}
|
||
|
|
Some(CSI_FREQ)
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
// Configure PLLs.
|
||
|
|
let pll_input = PllInput {
|
||
|
|
csi,
|
||
|
|
hse,
|
||
|
|
hsi,
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
source: config.pll_src,
|
||
|
|
};
|
||
|
|
let pll1 = init_pll(0, config.pll1, &pll_input);
|
||
|
|
let pll2 = init_pll(1, config.pll2, &pll_input);
|
||
|
|
#[cfg(any(rcc_h5, stm32h7))]
|
||
|
|
let _pll3 = init_pll(2, config.pll3, &pll_input);
|
||
|
|
|
||
|
|
// Configure sysclk
|
||
|
|
let (sys, sw) = match config.sys {
|
||
|
|
Sysclk::HSI => (unwrap!(hsi), Sw::HSI),
|
||
|
|
Sysclk::HSE => (unwrap!(hse), Sw::HSE),
|
||
|
|
Sysclk::CSI => (unwrap!(csi), Sw::CSI),
|
||
|
|
Sysclk::Pll1P => (unwrap!(pll1.p), Sw::PLL1),
|
||
|
|
};
|
||
|
|
|
||
|
|
// Check limits.
|
||
|
|
#[cfg(stm32h5)]
|
||
|
|
let (hclk_max, pclk_max) = match config.voltage_scale {
|
||
|
|
VoltageScale::Scale0 => (Hertz(250_000_000), Hertz(250_000_000)),
|
||
|
|
VoltageScale::Scale1 => (Hertz(200_000_000), Hertz(200_000_000)),
|
||
|
|
VoltageScale::Scale2 => (Hertz(150_000_000), Hertz(150_000_000)),
|
||
|
|
VoltageScale::Scale3 => (Hertz(100_000_000), Hertz(100_000_000)),
|
||
|
|
};
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
let (d1cpre_clk_max, hclk_max, pclk_max) = match config.voltage_scale {
|
||
|
|
VoltageScale::Scale0 => (Hertz(480_000_000), Hertz(240_000_000), Hertz(120_000_000)),
|
||
|
|
VoltageScale::Scale1 => (Hertz(400_000_000), Hertz(200_000_000), Hertz(100_000_000)),
|
||
|
|
VoltageScale::Scale2 => (Hertz(300_000_000), Hertz(150_000_000), Hertz(75_000_000)),
|
||
|
|
VoltageScale::Scale3 => (Hertz(200_000_000), Hertz(100_000_000), Hertz(50_000_000)),
|
||
|
|
};
|
||
|
|
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
let hclk = {
|
||
|
|
let d1cpre_clk = sys / config.d1c_pre;
|
||
|
|
assert!(d1cpre_clk <= d1cpre_clk_max);
|
||
|
|
sys / config.ahb_pre
|
||
|
|
};
|
||
|
|
#[cfg(stm32h5)]
|
||
|
|
let hclk = sys / config.ahb_pre;
|
||
|
|
assert!(hclk <= hclk_max);
|
||
|
|
|
||
|
|
let apb1 = hclk / config.apb1_pre;
|
||
|
|
let apb1_tim = apb_div_tim(&config.apb1_pre, hclk, config.timer_prescaler);
|
||
|
|
assert!(apb1 <= pclk_max);
|
||
|
|
let apb2 = hclk / config.apb2_pre;
|
||
|
|
let apb2_tim = apb_div_tim(&config.apb2_pre, hclk, config.timer_prescaler);
|
||
|
|
assert!(apb2 <= pclk_max);
|
||
|
|
let apb3 = hclk / config.apb3_pre;
|
||
|
|
assert!(apb3 <= pclk_max);
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
let apb4 = hclk / config.apb4_pre;
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
assert!(apb4 <= pclk_max);
|
||
|
|
|
||
|
|
let _per_ck = match config.per_clock_source {
|
||
|
|
Ckpersel::HSI => hsi,
|
||
|
|
Ckpersel::CSI => csi,
|
||
|
|
Ckpersel::HSE => hse,
|
||
|
|
_ => unreachable!(),
|
||
|
|
};
|
||
|
|
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
let adc = match config.adc_clock_source {
|
||
|
|
AdcClockSource::PLL2_P => pll2.p,
|
||
|
|
AdcClockSource::PLL3_R => _pll3.r,
|
||
|
|
AdcClockSource::PER => _per_ck,
|
||
|
|
_ => unreachable!(),
|
||
|
|
};
|
||
|
|
#[cfg(stm32h5)]
|
||
|
|
let adc = match config.adc_clock_source {
|
||
|
|
AdcClockSource::HCLK => Some(hclk),
|
||
|
|
AdcClockSource::SYSCLK => Some(sys),
|
||
|
|
AdcClockSource::PLL2_R => pll2.r,
|
||
|
|
AdcClockSource::HSE => hse,
|
||
|
|
AdcClockSource::HSI_KER => hsi,
|
||
|
|
AdcClockSource::CSI_KER => csi,
|
||
|
|
_ => unreachable!(),
|
||
|
|
};
|
||
|
|
|
||
|
|
flash_setup(hclk, config.voltage_scale);
|
||
|
|
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
{
|
||
|
|
RCC.d1cfgr().modify(|w| {
|
||
|
|
w.set_d1cpre(config.d1c_pre);
|
||
|
|
w.set_d1ppre(config.apb3_pre);
|
||
|
|
w.set_hpre(config.ahb_pre);
|
||
|
|
});
|
||
|
|
// Ensure core prescaler value is valid before future lower core voltage
|
||
|
|
while RCC.d1cfgr().read().d1cpre() != config.d1c_pre {}
|
||
|
|
|
||
|
|
RCC.d2cfgr().modify(|w| {
|
||
|
|
w.set_d2ppre1(config.apb1_pre);
|
||
|
|
w.set_d2ppre2(config.apb2_pre);
|
||
|
|
});
|
||
|
|
RCC.d3cfgr().modify(|w| {
|
||
|
|
w.set_d3ppre(config.apb4_pre);
|
||
|
|
});
|
||
|
|
|
||
|
|
RCC.d1ccipr().modify(|w| {
|
||
|
|
w.set_ckpersel(config.per_clock_source);
|
||
|
|
});
|
||
|
|
RCC.d3ccipr().modify(|w| {
|
||
|
|
w.set_adcsel(config.adc_clock_source);
|
||
|
|
});
|
||
|
|
}
|
||
|
|
#[cfg(stm32h5)]
|
||
|
|
{
|
||
|
|
// Set hpre
|
||
|
|
RCC.cfgr2().modify(|w| w.set_hpre(config.ahb_pre));
|
||
|
|
while RCC.cfgr2().read().hpre() != config.ahb_pre {}
|
||
|
|
|
||
|
|
// set ppre
|
||
|
|
RCC.cfgr2().modify(|w| {
|
||
|
|
w.set_ppre1(config.apb1_pre);
|
||
|
|
w.set_ppre2(config.apb2_pre);
|
||
|
|
w.set_ppre3(config.apb3_pre);
|
||
|
|
});
|
||
|
|
|
||
|
|
RCC.ccipr5().modify(|w| {
|
||
|
|
w.set_ckpersel(config.per_clock_source);
|
||
|
|
w.set_adcdacsel(config.adc_clock_source)
|
||
|
|
});
|
||
|
|
}
|
||
|
|
|
||
|
|
RCC.cfgr().modify(|w| w.set_timpre(config.timer_prescaler.into()));
|
||
|
|
|
||
|
|
RCC.cfgr().modify(|w| w.set_sw(sw));
|
||
|
|
while RCC.cfgr().read().sws() != sw {}
|
||
|
|
|
||
|
|
// IO compensation cell - Requires CSI clock and SYSCFG
|
||
|
|
#[cfg(stm32h7)] // TODO h5
|
||
|
|
if csi.is_some() {
|
||
|
|
// Enable the compensation cell, using back-bias voltage code
|
||
|
|
// provide by the cell.
|
||
|
|
critical_section::with(|_| {
|
||
|
|
pac::SYSCFG.cccsr().modify(|w| {
|
||
|
|
w.set_en(true);
|
||
|
|
w.set_cs(false);
|
||
|
|
w.set_hslv(false);
|
||
|
|
})
|
||
|
|
});
|
||
|
|
while !pac::SYSCFG.cccsr().read().ready() {}
|
||
|
|
}
|
||
|
|
|
||
|
|
set_freqs(Clocks {
|
||
|
|
sys,
|
||
|
|
ahb1: hclk,
|
||
|
|
ahb2: hclk,
|
||
|
|
ahb3: hclk,
|
||
|
|
ahb4: hclk,
|
||
|
|
apb1,
|
||
|
|
apb2,
|
||
|
|
apb3,
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
apb4,
|
||
|
|
apb1_tim,
|
||
|
|
apb2_tim,
|
||
|
|
adc: adc,
|
||
|
|
});
|
||
|
|
}
|
||
|
|
|
||
|
|
struct PllInput {
|
||
|
|
hsi: Option<Hertz>,
|
||
|
|
hse: Option<Hertz>,
|
||
|
|
csi: Option<Hertz>,
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
source: PllSource,
|
||
|
|
}
|
||
|
|
|
||
|
|
struct PllOutput {
|
||
|
|
p: Option<Hertz>,
|
||
|
|
#[allow(dead_code)]
|
||
|
|
q: Option<Hertz>,
|
||
|
|
#[allow(dead_code)]
|
||
|
|
r: Option<Hertz>,
|
||
|
|
}
|
||
|
|
|
||
|
|
fn init_pll(num: usize, config: Option<Pll>, input: &PllInput) -> PllOutput {
|
||
|
|
let Some(config) = config else {
|
||
|
|
// Stop PLL
|
||
|
|
RCC.cr().modify(|w| w.set_pllon(num, false));
|
||
|
|
while RCC.cr().read().pllrdy(num) {}
|
||
|
|
|
||
|
|
// "To save power when PLL1 is not used, the value of PLL1M must be set to 0.""
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
RCC.pllckselr().write(|w| w.set_divm(num, 0));
|
||
|
|
#[cfg(stm32h5)]
|
||
|
|
RCC.pllcfgr(num).write(|w| w.set_divm(0));
|
||
|
|
|
||
|
|
return PllOutput {
|
||
|
|
p: None,
|
||
|
|
q: None,
|
||
|
|
r: None,
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
assert!(1 <= config.prediv && config.prediv <= 63);
|
||
|
|
assert!(4 <= config.mul && config.mul <= 512);
|
||
|
|
|
||
|
|
#[cfg(stm32h5)]
|
||
|
|
let source = config.source;
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
let source = input.source;
|
||
|
|
|
||
|
|
let (in_clk, src) = match source {
|
||
|
|
PllSource::Hsi => (unwrap!(input.hsi), Pllsrc::HSI),
|
||
|
|
PllSource::Hse => (unwrap!(input.hse), Pllsrc::HSE),
|
||
|
|
PllSource::Csi => (unwrap!(input.csi), Pllsrc::CSI),
|
||
|
|
};
|
||
|
|
|
||
|
|
let ref_clk = in_clk / config.prediv as u32;
|
||
|
|
|
||
|
|
let ref_range = match ref_clk.0 {
|
||
|
|
..=1_999_999 => Pllrge::RANGE1,
|
||
|
|
..=3_999_999 => Pllrge::RANGE2,
|
||
|
|
..=7_999_999 => Pllrge::RANGE4,
|
||
|
|
..=16_000_000 => Pllrge::RANGE8,
|
||
|
|
x => panic!("pll ref_clk out of range: {} mhz", x),
|
||
|
|
};
|
||
|
|
|
||
|
|
// The smaller range (150 to 420 MHz) must
|
||
|
|
// be chosen when the reference clock frequency is lower than 2 MHz.
|
||
|
|
let wide_allowed = ref_range != Pllrge::RANGE1;
|
||
|
|
|
||
|
|
let vco_clk = ref_clk * config.mul;
|
||
|
|
let vco_range = if VCO_RANGE.contains(&vco_clk.0) {
|
||
|
|
Pllvcosel::MEDIUMVCO
|
||
|
|
} else if wide_allowed && VCO_WIDE_RANGE.contains(&vco_clk.0) {
|
||
|
|
Pllvcosel::WIDEVCO
|
||
|
|
} else {
|
||
|
|
panic!("pll vco_clk out of range: {} mhz", vco_clk.0)
|
||
|
|
};
|
||
|
|
|
||
|
|
let p = config.divp.map(|div| {
|
||
|
|
assert!(1 <= div && div <= 128);
|
||
|
|
if num == 0 {
|
||
|
|
// on PLL1, DIVP must be even.
|
||
|
|
assert!(div % 2 == 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
vco_clk / div
|
||
|
|
});
|
||
|
|
let q = config.divq.map(|div| {
|
||
|
|
assert!(1 <= div && div <= 128);
|
||
|
|
vco_clk / div
|
||
|
|
});
|
||
|
|
let r = config.divr.map(|div| {
|
||
|
|
assert!(1 <= div && div <= 128);
|
||
|
|
vco_clk / div
|
||
|
|
});
|
||
|
|
|
||
|
|
#[cfg(stm32h5)]
|
||
|
|
RCC.pllcfgr(num).write(|w| {
|
||
|
|
w.set_pllsrc(src);
|
||
|
|
w.set_divm(config.prediv);
|
||
|
|
w.set_pllvcosel(vco_range);
|
||
|
|
w.set_pllrge(ref_range);
|
||
|
|
w.set_pllfracen(false);
|
||
|
|
w.set_pllpen(p.is_some());
|
||
|
|
w.set_pllqen(q.is_some());
|
||
|
|
w.set_pllren(r.is_some());
|
||
|
|
});
|
||
|
|
|
||
|
|
#[cfg(stm32h7)]
|
||
|
|
{
|
||
|
|
RCC.pllckselr().modify(|w| {
|
||
|
|
w.set_divm(num, config.prediv);
|
||
|
|
w.set_pllsrc(src);
|
||
|
|
});
|
||
|
|
RCC.pllcfgr().modify(|w| {
|
||
|
|
w.set_pllvcosel(num, vco_range);
|
||
|
|
w.set_pllrge(num, ref_range);
|
||
|
|
w.set_pllfracen(num, false);
|
||
|
|
w.set_divpen(num, p.is_some());
|
||
|
|
w.set_divqen(num, q.is_some());
|
||
|
|
w.set_divren(num, r.is_some());
|
||
|
|
});
|
||
|
|
}
|
||
|
|
|
||
|
|
RCC.plldivr(num).write(|w| {
|
||
|
|
w.set_plln(config.mul - 1);
|
||
|
|
w.set_pllp((config.divp.unwrap_or(1) - 1) as u8);
|
||
|
|
w.set_pllq((config.divq.unwrap_or(1) - 1) as u8);
|
||
|
|
w.set_pllr((config.divr.unwrap_or(1) - 1) as u8);
|
||
|
|
});
|
||
|
|
|
||
|
|
RCC.cr().modify(|w| w.set_pllon(num, true));
|
||
|
|
while !RCC.cr().read().pllrdy(num) {}
|
||
|
|
|
||
|
|
PllOutput { p, q, r }
|
||
|
|
}
|
||
|
|
|
||
|
|
fn flash_setup(clk: Hertz, vos: VoltageScale) {
|
||
|
|
// RM0481 Rev 1, table 37
|
||
|
|
// LATENCY WRHIGHFREQ VOS3 VOS2 VOS1 VOS0
|
||
|
|
// 0 0 0 to 20 MHz 0 to 30 MHz 0 to 34 MHz 0 to 42 MHz
|
||
|
|
// 1 0 20 to 40 MHz 30 to 60 MHz 34 to 68 MHz 42 to 84 MHz
|
||
|
|
// 2 1 40 to 60 MHz 60 to 90 MHz 68 to 102 MHz 84 to 126 MHz
|
||
|
|
// 3 1 60 to 80 MHz 90 to 120 MHz 102 to 136 MHz 126 to 168 MHz
|
||
|
|
// 4 2 80 to 100 MHz 120 to 150 MHz 136 to 170 MHz 168 to 210 MHz
|
||
|
|
// 5 2 170 to 200 MHz 210 to 250 MHz
|
||
|
|
#[cfg(stm32h5)]
|
||
|
|
let (latency, wrhighfreq) = match (vos, clk.0) {
|
||
|
|
(VoltageScale::Scale0, ..=42_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale0, ..=84_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale0, ..=126_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale0, ..=168_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale0, ..=210_000_000) => (4, 2),
|
||
|
|
(VoltageScale::Scale0, ..=250_000_000) => (5, 2),
|
||
|
|
|
||
|
|
(VoltageScale::Scale1, ..=34_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale1, ..=68_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale1, ..=102_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale1, ..=136_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale1, ..=170_000_000) => (4, 2),
|
||
|
|
(VoltageScale::Scale1, ..=200_000_000) => (5, 2),
|
||
|
|
|
||
|
|
(VoltageScale::Scale2, ..=30_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale2, ..=60_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale2, ..=90_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale2, ..=120_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale2, ..=150_000_000) => (4, 2),
|
||
|
|
|
||
|
|
(VoltageScale::Scale3, ..=20_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale3, ..=40_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale3, ..=60_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale3, ..=80_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale3, ..=100_000_000) => (4, 2),
|
||
|
|
|
||
|
|
_ => unreachable!(),
|
||
|
|
};
|
||
|
|
|
||
|
|
#[cfg(flash_h7)]
|
||
|
|
let (latency, wrhighfreq) = match (vos, clk.0) {
|
||
|
|
// VOS 0 range VCORE 1.26V - 1.40V
|
||
|
|
(VoltageScale::Scale0, ..=70_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale0, ..=140_000_000) => (1, 1),
|
||
|
|
(VoltageScale::Scale0, ..=185_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale0, ..=210_000_000) => (2, 2),
|
||
|
|
(VoltageScale::Scale0, ..=225_000_000) => (3, 2),
|
||
|
|
(VoltageScale::Scale0, ..=240_000_000) => (4, 2),
|
||
|
|
// VOS 1 range VCORE 1.15V - 1.26V
|
||
|
|
(VoltageScale::Scale1, ..=70_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale1, ..=140_000_000) => (1, 1),
|
||
|
|
(VoltageScale::Scale1, ..=185_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale1, ..=210_000_000) => (2, 2),
|
||
|
|
(VoltageScale::Scale1, ..=225_000_000) => (3, 2),
|
||
|
|
// VOS 2 range VCORE 1.05V - 1.15V
|
||
|
|
(VoltageScale::Scale2, ..=55_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale2, ..=110_000_000) => (1, 1),
|
||
|
|
(VoltageScale::Scale2, ..=165_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale2, ..=224_000_000) => (3, 2),
|
||
|
|
// VOS 3 range VCORE 0.95V - 1.05V
|
||
|
|
(VoltageScale::Scale3, ..=45_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale3, ..=90_000_000) => (1, 1),
|
||
|
|
(VoltageScale::Scale3, ..=135_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale3, ..=180_000_000) => (3, 2),
|
||
|
|
(VoltageScale::Scale3, ..=224_000_000) => (4, 2),
|
||
|
|
_ => unreachable!(),
|
||
|
|
};
|
||
|
|
|
||
|
|
// See RM0455 Rev 10 Table 16. FLASH recommended number of wait
|
||
|
|
// states and programming delay
|
||
|
|
#[cfg(flash_h7ab)]
|
||
|
|
let (latency, wrhighfreq) = match (vos, clk.0) {
|
||
|
|
// VOS 0 range VCORE 1.25V - 1.35V
|
||
|
|
(VoltageScale::Scale0, ..=42_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale0, ..=84_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale0, ..=126_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale0, ..=168_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale0, ..=210_000_000) => (4, 2),
|
||
|
|
(VoltageScale::Scale0, ..=252_000_000) => (5, 2),
|
||
|
|
(VoltageScale::Scale0, ..=280_000_000) => (6, 3),
|
||
|
|
// VOS 1 range VCORE 1.15V - 1.25V
|
||
|
|
(VoltageScale::Scale1, ..=38_000_000) => (0, 0),
|
||
|
|
(VoltageScale::Scale1, ..=76_000_000) => (1, 0),
|
||
|
|
(VoltageScale::Scale1, ..=114_000_000) => (2, 1),
|
||
|
|
(VoltageScale::Scale1, ..=152_000_000) => (3, 1),
|
||
|
|
(VoltageScale::Scale1, ..=190_000_000) => (4, 2),
|
||
|
|
(VoltageScale::Scale1, ..=225_000_000) => (5, 2),
|
||
|
|
// VOS 2 range VCORE 1.05V - 1.15V
|
||
|
|
(VoltageScale::Scale2, ..=34) => (0, 0),
|
||
|
|
(VoltageScale::Scale2, ..=68) => (1, 0),
|
||
|
|
(VoltageScale::Scale2, ..=102) => (2, 1),
|
||
|
|
(VoltageScale::Scale2, ..=136) => (3, 1),
|
||
|
|
(VoltageScale::Scale2, ..=160) => (4, 2),
|
||
|
|
// VOS 3 range VCORE 0.95V - 1.05V
|
||
|
|
(VoltageScale::Scale3, ..=22) => (0, 0),
|
||
|
|
(VoltageScale::Scale3, ..=44) => (1, 0),
|
||
|
|
(VoltageScale::Scale3, ..=66) => (2, 1),
|
||
|
|
(VoltageScale::Scale3, ..=88) => (3, 1),
|
||
|
|
_ => unreachable!(),
|
||
|
|
};
|
||
|
|
|
||
|
|
debug!("flash: latency={} wrhighfreq={}", latency, wrhighfreq);
|
||
|
|
|
||
|
|
FLASH.acr().write(|w| {
|
||
|
|
w.set_wrhighfreq(wrhighfreq);
|
||
|
|
w.set_latency(latency);
|
||
|
|
});
|
||
|
|
while FLASH.acr().read().latency() != latency {}
|
||
|
|
}
|