2021-06-25 06:23:46 +02:00
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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2021-07-29 13:44:51 +02:00
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use embassy_hal_common::unborrow;
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2021-06-25 06:23:46 +02:00
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use embedded_hal::blocking::spi as eh;
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2021-06-30 23:43:40 +02:00
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use embedded_hal::spi as ehnb;
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2021-06-25 06:23:46 +02:00
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2021-06-25 18:17:59 +02:00
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{NoPin, OptionalPin};
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use crate::{pac, peripherals};
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2021-06-25 06:23:46 +02:00
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2021-06-30 23:43:40 +02:00
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pub use ehnb::{Phase, Polarity};
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2021-06-25 06:23:46 +02:00
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#[non_exhaustive]
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pub struct Config {
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pub frequency: u32,
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2021-06-30 23:43:40 +02:00
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pub phase: ehnb::Phase,
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pub polarity: ehnb::Polarity,
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2021-06-25 06:23:46 +02:00
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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frequency: 1_000_000,
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2021-06-30 23:43:40 +02:00
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phase: ehnb::Phase::CaptureOnFirstTransition,
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polarity: ehnb::Polarity::IdleLow,
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2021-06-25 06:23:46 +02:00
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}
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}
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}
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pub struct Spi<'d, T: Instance> {
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inner: T,
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phantom: PhantomData<&'d mut T>,
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}
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2021-07-12 02:45:59 +02:00
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fn div_roundup(a: u32, b: u32) -> u32 {
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(a + b - 1) / b
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}
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fn calc_prescs(freq: u32) -> (u8, u8) {
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let clk_peri = crate::clocks::clk_peri_freq();
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// final SPI frequency: spi_freq = clk_peri / presc / postdiv
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// presc must be in 2..=254, and must be even
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// postdiv must be in 1..=256
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// divide extra by 2, so we get rid of the "presc must be even" requirement
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let ratio = div_roundup(clk_peri, freq * 2);
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if ratio > 127 * 256 {
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panic!("Requested too low SPI frequency");
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}
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let presc = div_roundup(ratio, 256);
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let postdiv = if presc == 1 {
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ratio
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} else {
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div_roundup(ratio, presc)
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};
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((presc * 2) as u8, (postdiv - 1) as u8)
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}
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2021-06-25 06:23:46 +02:00
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impl<'d, T: Instance> Spi<'d, T> {
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pub fn new(
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inner: impl Unborrow<Target = T>,
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clk: impl Unborrow<Target = impl ClkPin<T>>,
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mosi: impl Unborrow<Target = impl MosiPin<T>>,
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miso: impl Unborrow<Target = impl MisoPin<T>>,
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cs: impl Unborrow<Target = impl CsPin<T>>,
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config: Config,
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) -> Self {
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unborrow!(inner, clk, mosi, miso, cs);
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2021-06-25 06:23:46 +02:00
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unsafe {
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let p = inner.regs();
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2021-07-12 02:45:59 +02:00
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let (presc, postdiv) = calc_prescs(config.frequency);
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2021-07-12 02:45:59 +02:00
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().write(|w| {
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w.set_dss(0b0111); // 8bit
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2021-06-30 23:43:40 +02:00
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w.set_spo(config.polarity == ehnb::Polarity::IdleHigh);
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w.set_sph(config.phase == ehnb::Phase::CaptureOnSecondTransition);
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w.set_scr(postdiv);
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});
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p.cr1().write(|w| {
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w.set_sse(true); // enable
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});
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2021-06-25 18:17:59 +02:00
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if let Some(pin) = clk.pin_mut() {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = mosi.pin_mut() {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = miso.pin_mut() {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = cs.pin_mut() {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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}
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Self {
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inner,
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phantom: PhantomData,
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}
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}
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pub fn write(&mut self, data: &[u8]) {
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unsafe {
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let p = self.inner.regs();
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for &b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(b as _));
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2021-07-20 09:42:52 +02:00
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while !p.sr().read().rne() {}
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let _ = p.dr().read();
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2021-06-25 06:23:46 +02:00
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}
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self.flush();
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}
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}
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2021-06-30 23:43:22 +02:00
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pub fn transfer(&mut self, data: &mut [u8]) {
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unsafe {
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let p = self.inner.regs();
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for b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(*b as _));
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while !p.sr().read().rne() {}
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*b = p.dr().read().data() as u8;
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}
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self.flush();
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}
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}
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2021-06-25 06:23:46 +02:00
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pub fn flush(&mut self) {
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unsafe {
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let p = self.inner.regs();
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while p.sr().read().bsy() {}
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}
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}
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2021-07-12 02:45:59 +02:00
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pub fn set_frequency(&mut self, freq: u32) {
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let (presc, postdiv) = calc_prescs(freq);
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let p = self.inner.regs();
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unsafe {
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2021-07-20 09:43:06 +02:00
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// disable
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p.cr1().write(|w| w.set_sse(false));
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// change stuff
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().modify(|w| {
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w.set_scr(postdiv);
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});
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2021-07-20 09:43:06 +02:00
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// enable
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p.cr1().write(|w| w.set_sse(true));
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}
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}
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2021-06-25 06:23:46 +02:00
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}
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impl<'d, T: Instance> eh::Write<u8> for Spi<'d, T> {
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type Error = core::convert::Infallible;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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self.write(words);
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Ok(())
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}
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}
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2021-06-30 23:43:22 +02:00
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impl<'d, T: Instance> eh::Transfer<u8> for Spi<'d, T> {
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type Error = core::convert::Infallible;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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self.transfer(words);
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Ok(words)
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}
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}
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2021-06-25 06:23:46 +02:00
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mod sealed {
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use super::*;
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pub trait Instance {
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fn regs(&self) -> pac::spi::Spi;
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}
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pub trait ClkPin<T: Instance> {}
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pub trait CsPin<T: Instance> {}
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pub trait MosiPin<T: Instance> {}
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pub trait MisoPin<T: Instance> {}
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}
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pub trait Instance: sealed::Instance {}
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macro_rules! impl_instance {
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($type:ident, $irq:ident) => {
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impl sealed::Instance for peripherals::$type {
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fn regs(&self) -> pac::spi::Spi {
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pac::$type
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}
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}
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impl Instance for peripherals::$type {}
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};
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}
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impl_instance!(SPI0, Spi0);
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impl_instance!(SPI1, Spi1);
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2021-06-25 18:17:59 +02:00
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pub trait ClkPin<T: Instance>: sealed::ClkPin<T> + OptionalPin {}
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pub trait CsPin<T: Instance>: sealed::CsPin<T> + OptionalPin {}
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pub trait MosiPin<T: Instance>: sealed::MosiPin<T> + OptionalPin {}
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pub trait MisoPin<T: Instance>: sealed::MisoPin<T> + OptionalPin {}
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impl<T: Instance> sealed::ClkPin<T> for NoPin {}
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impl<T: Instance> ClkPin<T> for NoPin {}
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impl<T: Instance> sealed::CsPin<T> for NoPin {}
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impl<T: Instance> CsPin<T> for NoPin {}
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impl<T: Instance> sealed::MosiPin<T> for NoPin {}
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impl<T: Instance> MosiPin<T> for NoPin {}
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impl<T: Instance> sealed::MisoPin<T> for NoPin {}
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impl<T: Instance> MisoPin<T> for NoPin {}
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2021-06-25 06:23:46 +02:00
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macro_rules! impl_pin {
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($pin:ident, $instance:ident, $function:ident) => {
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impl sealed::$function<peripherals::$instance> for peripherals::$pin {}
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impl $function<peripherals::$instance> for peripherals::$pin {}
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};
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}
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impl_pin!(PIN_0, SPI0, MisoPin);
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impl_pin!(PIN_1, SPI0, CsPin);
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impl_pin!(PIN_2, SPI0, ClkPin);
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impl_pin!(PIN_3, SPI0, MosiPin);
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impl_pin!(PIN_4, SPI0, MisoPin);
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impl_pin!(PIN_5, SPI0, CsPin);
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impl_pin!(PIN_6, SPI0, ClkPin);
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impl_pin!(PIN_7, SPI0, MosiPin);
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impl_pin!(PIN_8, SPI1, MisoPin);
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impl_pin!(PIN_9, SPI1, CsPin);
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impl_pin!(PIN_10, SPI1, ClkPin);
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impl_pin!(PIN_11, SPI1, MosiPin);
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impl_pin!(PIN_12, SPI1, MisoPin);
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impl_pin!(PIN_13, SPI1, CsPin);
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impl_pin!(PIN_14, SPI1, ClkPin);
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impl_pin!(PIN_15, SPI1, MosiPin);
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impl_pin!(PIN_16, SPI0, MisoPin);
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impl_pin!(PIN_17, SPI0, CsPin);
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impl_pin!(PIN_18, SPI0, ClkPin);
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impl_pin!(PIN_19, SPI0, MosiPin);
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