2021-01-18 14:22:55 +01:00
|
|
|
#![no_std]
|
|
|
|
#![no_main]
|
|
|
|
#![feature(type_alias_impl_trait)]
|
|
|
|
|
|
|
|
#[path = "../example_common.rs"]
|
|
|
|
mod example_common;
|
|
|
|
|
2021-03-29 02:47:10 +02:00
|
|
|
use embassy::executor::Spawner;
|
2021-03-21 21:58:59 +01:00
|
|
|
use embassy_nrf::gpio::{Level, Output, OutputDrive};
|
2021-03-29 02:47:10 +02:00
|
|
|
use embassy_nrf::Peripherals;
|
|
|
|
use embassy_nrf::{interrupt, spim};
|
2021-03-21 21:58:59 +01:00
|
|
|
use embassy_traits::spi::FullDuplex;
|
|
|
|
use example_common::*;
|
2021-01-18 14:22:55 +01:00
|
|
|
|
2021-03-29 02:47:10 +02:00
|
|
|
#[embassy::main]
|
2021-05-17 11:48:58 +02:00
|
|
|
async fn main(_spawner: Spawner, p: Peripherals) {
|
2021-01-18 14:22:55 +01:00
|
|
|
info!("running!");
|
|
|
|
|
2021-05-11 03:04:59 +02:00
|
|
|
let mut config = spim::Config::default();
|
|
|
|
config.frequency = spim::Frequency::M16;
|
2021-01-18 14:22:55 +01:00
|
|
|
|
2021-03-21 21:58:59 +01:00
|
|
|
let irq = interrupt::take!(SPIM3);
|
2021-05-11 03:04:59 +02:00
|
|
|
let mut spim = spim::Spim::new(p.SPI3, irq, p.P0_29, p.P0_28, p.P0_30, config);
|
2021-01-18 14:22:55 +01:00
|
|
|
|
2021-03-27 03:12:58 +01:00
|
|
|
let mut ncs = Output::new(p.P0_31, Level::High, OutputDrive::Standard);
|
2021-03-19 04:08:44 +01:00
|
|
|
|
2021-01-18 14:22:55 +01:00
|
|
|
// Example on how to talk to an ENC28J60 chip
|
|
|
|
|
|
|
|
// softreset
|
|
|
|
cortex_m::asm::delay(10);
|
2021-12-19 23:25:02 +01:00
|
|
|
ncs.set_low();
|
2021-01-18 14:22:55 +01:00
|
|
|
cortex_m::asm::delay(5);
|
|
|
|
let tx = [0xFF];
|
2021-04-14 16:37:10 +02:00
|
|
|
unwrap!(spim.read_write(&mut [], &tx).await);
|
2021-01-18 14:22:55 +01:00
|
|
|
cortex_m::asm::delay(10);
|
2021-12-19 23:25:02 +01:00
|
|
|
ncs.set_high();
|
2021-01-18 14:22:55 +01:00
|
|
|
|
|
|
|
cortex_m::asm::delay(100000);
|
|
|
|
|
|
|
|
let mut rx = [0; 2];
|
|
|
|
|
|
|
|
// read ESTAT
|
|
|
|
cortex_m::asm::delay(5000);
|
2021-12-19 23:25:02 +01:00
|
|
|
ncs.set_low();
|
2021-01-18 14:22:55 +01:00
|
|
|
cortex_m::asm::delay(5000);
|
|
|
|
let tx = [0b000_11101, 0];
|
2021-04-14 16:37:10 +02:00
|
|
|
unwrap!(spim.read_write(&mut rx, &tx).await);
|
2021-01-18 14:22:55 +01:00
|
|
|
cortex_m::asm::delay(5000);
|
2021-12-19 23:25:02 +01:00
|
|
|
ncs.set_high();
|
2021-01-18 14:22:55 +01:00
|
|
|
info!("estat: {=[?]}", rx);
|
|
|
|
|
|
|
|
// Switch to bank 3
|
|
|
|
cortex_m::asm::delay(10);
|
2021-12-19 23:25:02 +01:00
|
|
|
ncs.set_low();
|
2021-01-18 14:22:55 +01:00
|
|
|
cortex_m::asm::delay(5);
|
|
|
|
let tx = [0b100_11111, 0b11];
|
2021-04-14 16:37:10 +02:00
|
|
|
unwrap!(spim.read_write(&mut rx, &tx).await);
|
2021-01-18 14:22:55 +01:00
|
|
|
cortex_m::asm::delay(10);
|
2021-12-19 23:25:02 +01:00
|
|
|
ncs.set_high();
|
2021-01-18 14:22:55 +01:00
|
|
|
|
|
|
|
// read EREVID
|
|
|
|
cortex_m::asm::delay(10);
|
2021-12-19 23:25:02 +01:00
|
|
|
ncs.set_low();
|
2021-01-18 14:22:55 +01:00
|
|
|
cortex_m::asm::delay(5);
|
|
|
|
let tx = [0b000_10010, 0];
|
2021-04-14 16:37:10 +02:00
|
|
|
unwrap!(spim.read_write(&mut rx, &tx).await);
|
2021-01-18 14:22:55 +01:00
|
|
|
cortex_m::asm::delay(10);
|
2021-12-19 23:25:02 +01:00
|
|
|
ncs.set_high();
|
2021-01-18 14:22:55 +01:00
|
|
|
|
|
|
|
info!("erevid: {=[?]}", rx);
|
|
|
|
}
|