2022-09-26 15:28:09 +02:00
|
|
|
use core::cell::RefCell;
|
2022-09-22 16:42:49 +02:00
|
|
|
use core::future::{poll_fn, Future};
|
2022-05-04 20:48:37 +02:00
|
|
|
use core::task::Poll;
|
2022-06-12 22:15:44 +02:00
|
|
|
|
|
|
|
use atomic_polyfill::{compiler_fence, Ordering};
|
2022-06-11 05:08:57 +02:00
|
|
|
use embassy_cortex_m::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
|
2022-05-04 20:48:37 +02:00
|
|
|
use embassy_hal_common::ring_buffer::RingBuffer;
|
2022-08-22 21:46:09 +02:00
|
|
|
use embassy_sync::waitqueue::WakerRegistration;
|
2022-05-04 20:48:37 +02:00
|
|
|
|
|
|
|
use super::*;
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
pub struct State<'d, T: BasicInstance>(StateStorage<StateInner<'d, T>>);
|
|
|
|
impl<'d, T: BasicInstance> State<'d, T> {
|
2022-09-15 12:34:17 +02:00
|
|
|
pub const fn new() -> Self {
|
2022-05-04 20:48:37 +02:00
|
|
|
Self(StateStorage::new())
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
struct StateInner<'d, T: BasicInstance> {
|
2022-05-04 20:48:37 +02:00
|
|
|
phantom: PhantomData<&'d mut T>,
|
|
|
|
|
|
|
|
rx_waker: WakerRegistration,
|
|
|
|
rx: RingBuffer<'d>,
|
|
|
|
|
|
|
|
tx_waker: WakerRegistration,
|
|
|
|
tx: RingBuffer<'d>,
|
|
|
|
}
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
unsafe impl<'d, T: BasicInstance> Send for StateInner<'d, T> {}
|
|
|
|
unsafe impl<'d, T: BasicInstance> Sync for StateInner<'d, T> {}
|
2022-05-04 20:48:37 +02:00
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
pub struct BufferedUart<'d, T: BasicInstance> {
|
2022-09-26 15:28:09 +02:00
|
|
|
inner: RefCell<PeripheralMutex<'d, StateInner<'d, T>>>,
|
|
|
|
}
|
|
|
|
|
|
|
|
pub struct BufferedUartTx<'u, 'd, T: BasicInstance> {
|
|
|
|
inner: &'u BufferedUart<'d, T>,
|
|
|
|
}
|
|
|
|
|
|
|
|
pub struct BufferedUartRx<'u, 'd, T: BasicInstance> {
|
|
|
|
inner: &'u BufferedUart<'d, T>,
|
2022-05-04 20:48:37 +02:00
|
|
|
}
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
impl<'d, T: BasicInstance> Unpin for BufferedUart<'d, T> {}
|
2022-05-04 20:48:37 +02:00
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
impl<'d, T: BasicInstance> BufferedUart<'d, T> {
|
2022-06-09 21:28:13 +02:00
|
|
|
pub fn new(
|
2022-05-04 20:48:37 +02:00
|
|
|
state: &'d mut State<'d, T>,
|
2022-10-27 11:03:37 +02:00
|
|
|
peri: impl Peripheral<P = T> + 'd,
|
2022-10-26 18:58:22 +02:00
|
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
|
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
2022-07-23 14:00:19 +02:00
|
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
2022-05-04 20:48:37 +02:00
|
|
|
tx_buffer: &'d mut [u8],
|
|
|
|
rx_buffer: &'d mut [u8],
|
2022-10-26 18:58:22 +02:00
|
|
|
config: Config,
|
2022-05-04 20:48:37 +02:00
|
|
|
) -> BufferedUart<'d, T> {
|
2022-10-27 11:03:37 +02:00
|
|
|
T::enable();
|
|
|
|
T::reset();
|
|
|
|
|
|
|
|
Self::new_inner(state, peri, rx, tx, irq, tx_buffer, rx_buffer, config)
|
|
|
|
}
|
|
|
|
|
|
|
|
pub fn new_with_rtscts(
|
|
|
|
state: &'d mut State<'d, T>,
|
|
|
|
peri: impl Peripheral<P = T> + 'd,
|
|
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
|
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
|
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
|
|
|
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
|
|
|
|
cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
|
|
|
|
tx_buffer: &'d mut [u8],
|
|
|
|
rx_buffer: &'d mut [u8],
|
|
|
|
config: Config,
|
|
|
|
) -> BufferedUart<'d, T> {
|
|
|
|
into_ref!(cts, rts);
|
2022-10-26 18:58:22 +02:00
|
|
|
|
|
|
|
T::enable();
|
|
|
|
T::reset();
|
2022-05-04 20:48:37 +02:00
|
|
|
|
2022-10-27 11:03:37 +02:00
|
|
|
unsafe {
|
|
|
|
rts.set_as_af(rts.af_num(), AFType::OutputPushPull);
|
|
|
|
cts.set_as_af(cts.af_num(), AFType::Input);
|
|
|
|
T::regs().cr3().write(|w| {
|
|
|
|
w.set_rtse(true);
|
|
|
|
w.set_ctse(true);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
Self::new_inner(state, peri, rx, tx, irq, tx_buffer, rx_buffer, config)
|
|
|
|
}
|
|
|
|
|
|
|
|
fn new_inner(
|
|
|
|
state: &'d mut State<'d, T>,
|
|
|
|
_peri: impl Peripheral<P = T> + 'd,
|
|
|
|
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
|
|
|
|
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
|
|
|
|
irq: impl Peripheral<P = T::Interrupt> + 'd,
|
|
|
|
tx_buffer: &'d mut [u8],
|
|
|
|
rx_buffer: &'d mut [u8],
|
|
|
|
config: Config,
|
|
|
|
) -> BufferedUart<'d, T> {
|
|
|
|
into_ref!(_peri, rx, tx, irq);
|
|
|
|
|
2022-05-04 20:48:37 +02:00
|
|
|
let r = T::regs();
|
2022-10-26 18:58:22 +02:00
|
|
|
|
2022-06-09 21:28:13 +02:00
|
|
|
unsafe {
|
2022-10-26 18:58:22 +02:00
|
|
|
rx.set_as_af(rx.af_num(), AFType::Input);
|
|
|
|
tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
|
2022-10-28 09:32:05 +02:00
|
|
|
}
|
2022-10-26 18:58:22 +02:00
|
|
|
|
2022-10-28 09:32:05 +02:00
|
|
|
configure(r, &config, T::frequency(), T::MULTIPLIER, true, true);
|
|
|
|
|
|
|
|
unsafe {
|
|
|
|
r.cr1().modify(|w| {
|
2022-06-09 21:28:13 +02:00
|
|
|
w.set_rxneie(true);
|
|
|
|
w.set_idleie(true);
|
|
|
|
});
|
|
|
|
}
|
2022-05-04 20:48:37 +02:00
|
|
|
|
|
|
|
Self {
|
2022-09-26 15:28:09 +02:00
|
|
|
inner: RefCell::new(PeripheralMutex::new(irq, &mut state.0, move || StateInner {
|
2022-05-04 20:48:37 +02:00
|
|
|
phantom: PhantomData,
|
|
|
|
tx: RingBuffer::new(tx_buffer),
|
|
|
|
tx_waker: WakerRegistration::new(),
|
|
|
|
|
|
|
|
rx: RingBuffer::new(rx_buffer),
|
|
|
|
rx_waker: WakerRegistration::new(),
|
2022-09-26 15:28:09 +02:00
|
|
|
})),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pub fn split<'u>(&'u mut self) -> (BufferedUartRx<'u, 'd, T>, BufferedUartTx<'u, 'd, T>) {
|
|
|
|
(BufferedUartRx { inner: self }, BufferedUartTx { inner: self })
|
|
|
|
}
|
|
|
|
|
|
|
|
async fn inner_read<'a>(&'a self, buf: &'a mut [u8]) -> Result<usize, Error> {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
let mut do_pend = false;
|
|
|
|
let mut inner = self.inner.borrow_mut();
|
|
|
|
let res = inner.with(|state| {
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
|
|
|
|
// We have data ready in buffer? Return it.
|
|
|
|
let data = state.rx.pop_buf();
|
|
|
|
if !data.is_empty() {
|
|
|
|
let len = data.len().min(buf.len());
|
|
|
|
buf[..len].copy_from_slice(&data[..len]);
|
|
|
|
|
|
|
|
if state.rx.is_full() {
|
|
|
|
do_pend = true;
|
|
|
|
}
|
|
|
|
state.rx.pop(len);
|
|
|
|
|
|
|
|
return Poll::Ready(Ok(len));
|
|
|
|
}
|
|
|
|
|
|
|
|
state.rx_waker.register(cx.waker());
|
|
|
|
Poll::Pending
|
|
|
|
});
|
|
|
|
|
|
|
|
if do_pend {
|
|
|
|
inner.pend();
|
|
|
|
}
|
|
|
|
|
|
|
|
res
|
|
|
|
})
|
|
|
|
.await
|
|
|
|
}
|
|
|
|
|
|
|
|
async fn inner_write<'a>(&'a self, buf: &'a [u8]) -> Result<usize, Error> {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
let mut inner = self.inner.borrow_mut();
|
|
|
|
let (poll, empty) = inner.with(|state| {
|
|
|
|
let empty = state.tx.is_empty();
|
|
|
|
let tx_buf = state.tx.push_buf();
|
|
|
|
if tx_buf.is_empty() {
|
|
|
|
state.tx_waker.register(cx.waker());
|
|
|
|
return (Poll::Pending, empty);
|
|
|
|
}
|
|
|
|
|
|
|
|
let n = core::cmp::min(tx_buf.len(), buf.len());
|
|
|
|
tx_buf[..n].copy_from_slice(&buf[..n]);
|
|
|
|
state.tx.push(n);
|
|
|
|
|
|
|
|
(Poll::Ready(Ok(n)), empty)
|
|
|
|
});
|
|
|
|
if empty {
|
|
|
|
inner.pend();
|
|
|
|
}
|
|
|
|
poll
|
|
|
|
})
|
|
|
|
.await
|
|
|
|
}
|
|
|
|
|
|
|
|
async fn inner_flush<'a>(&'a self) -> Result<(), Error> {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
self.inner.borrow_mut().with(|state| {
|
|
|
|
if !state.tx.is_empty() {
|
|
|
|
state.tx_waker.register(cx.waker());
|
|
|
|
return Poll::Pending;
|
|
|
|
}
|
|
|
|
|
|
|
|
Poll::Ready(Ok(()))
|
|
|
|
})
|
|
|
|
})
|
|
|
|
.await
|
|
|
|
}
|
|
|
|
|
|
|
|
async fn inner_fill_buf<'a>(&'a self) -> Result<&'a [u8], Error> {
|
|
|
|
poll_fn(move |cx| {
|
|
|
|
self.inner.borrow_mut().with(|state| {
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
|
|
|
|
// We have data ready in buffer? Return it.
|
|
|
|
let buf = state.rx.pop_buf();
|
|
|
|
if !buf.is_empty() {
|
|
|
|
let buf: &[u8] = buf;
|
|
|
|
// Safety: buffer lives as long as uart
|
|
|
|
let buf: &[u8] = unsafe { core::mem::transmute(buf) };
|
|
|
|
return Poll::Ready(Ok(buf));
|
|
|
|
}
|
|
|
|
|
|
|
|
state.rx_waker.register(cx.waker());
|
|
|
|
Poll::<Result<&[u8], Error>>::Pending
|
|
|
|
})
|
|
|
|
})
|
|
|
|
.await
|
|
|
|
}
|
|
|
|
|
|
|
|
fn inner_consume(&self, amt: usize) {
|
|
|
|
let mut inner = self.inner.borrow_mut();
|
|
|
|
let signal = inner.with(|state| {
|
|
|
|
let full = state.rx.is_full();
|
|
|
|
state.rx.pop(amt);
|
|
|
|
full
|
|
|
|
});
|
|
|
|
if signal {
|
|
|
|
inner.pend();
|
2022-05-04 20:48:37 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
impl<'d, T: BasicInstance> StateInner<'d, T>
|
2022-05-04 20:48:37 +02:00
|
|
|
where
|
|
|
|
Self: 'd,
|
|
|
|
{
|
|
|
|
fn on_rx(&mut self) {
|
|
|
|
let r = T::regs();
|
|
|
|
unsafe {
|
|
|
|
let sr = sr(r).read();
|
|
|
|
clear_interrupt_flags(r, sr);
|
|
|
|
|
|
|
|
// This read also clears the error and idle interrupt flags on v1.
|
|
|
|
let b = rdr(r).read_volatile();
|
|
|
|
|
|
|
|
if sr.rxne() {
|
|
|
|
if sr.pe() {
|
|
|
|
warn!("Parity error");
|
|
|
|
}
|
|
|
|
if sr.fe() {
|
|
|
|
warn!("Framing error");
|
|
|
|
}
|
|
|
|
if sr.ne() {
|
|
|
|
warn!("Noise error");
|
|
|
|
}
|
|
|
|
if sr.ore() {
|
|
|
|
warn!("Overrun error");
|
|
|
|
}
|
|
|
|
|
|
|
|
let buf = self.rx.push_buf();
|
|
|
|
if !buf.is_empty() {
|
|
|
|
buf[0] = b;
|
|
|
|
self.rx.push(1);
|
|
|
|
} else {
|
|
|
|
warn!("RX buffer full, discard received byte");
|
|
|
|
}
|
|
|
|
|
|
|
|
if self.rx.is_full() {
|
|
|
|
self.rx_waker.wake();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if sr.idle() {
|
|
|
|
self.rx_waker.wake();
|
|
|
|
};
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn on_tx(&mut self) {
|
|
|
|
let r = T::regs();
|
|
|
|
unsafe {
|
|
|
|
if sr(r).read().txe() {
|
|
|
|
let buf = self.tx.pop_buf();
|
|
|
|
if !buf.is_empty() {
|
|
|
|
r.cr1().modify(|w| {
|
|
|
|
w.set_txeie(true);
|
|
|
|
});
|
|
|
|
tdr(r).write_volatile(buf[0].into());
|
|
|
|
self.tx.pop(1);
|
|
|
|
self.tx_waker.wake();
|
|
|
|
} else {
|
|
|
|
// Disable interrupt until we have something to transmit again
|
|
|
|
r.cr1().modify(|w| {
|
|
|
|
w.set_txeie(false);
|
|
|
|
});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
impl<'d, T: BasicInstance> PeripheralState for StateInner<'d, T>
|
2022-05-04 20:48:37 +02:00
|
|
|
where
|
|
|
|
Self: 'd,
|
|
|
|
{
|
|
|
|
type Interrupt = T::Interrupt;
|
|
|
|
fn on_interrupt(&mut self) {
|
|
|
|
self.on_rx();
|
|
|
|
self.on_tx();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl embedded_io::Error for Error {
|
|
|
|
fn kind(&self) -> embedded_io::ErrorKind {
|
|
|
|
embedded_io::ErrorKind::Other
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
impl<'d, T: BasicInstance> embedded_io::Io for BufferedUart<'d, T> {
|
2022-05-04 20:48:37 +02:00
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-09-26 15:28:09 +02:00
|
|
|
impl<'u, 'd, T: BasicInstance> embedded_io::Io for BufferedUartRx<'u, 'd, T> {
|
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'u, 'd, T: BasicInstance> embedded_io::Io for BufferedUartTx<'u, 'd, T> {
|
|
|
|
type Error = Error;
|
|
|
|
}
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
impl<'d, T: BasicInstance> embedded_io::asynch::Read for BufferedUart<'d, T> {
|
2022-10-26 16:47:29 +02:00
|
|
|
type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a
|
2022-05-04 20:48:37 +02:00
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
2022-09-26 15:28:09 +02:00
|
|
|
self.inner_read(buf)
|
|
|
|
}
|
|
|
|
}
|
2022-05-04 20:48:37 +02:00
|
|
|
|
2022-09-26 15:28:09 +02:00
|
|
|
impl<'u, 'd, T: BasicInstance> embedded_io::asynch::Read for BufferedUartRx<'u, 'd, T> {
|
2022-10-26 16:47:29 +02:00
|
|
|
type ReadFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a
|
2022-09-26 15:28:09 +02:00
|
|
|
where
|
|
|
|
Self: 'a;
|
2022-05-04 20:48:37 +02:00
|
|
|
|
2022-09-26 15:28:09 +02:00
|
|
|
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
|
|
self.inner.inner_read(buf)
|
2022-05-04 20:48:37 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
impl<'d, T: BasicInstance> embedded_io::asynch::BufRead for BufferedUart<'d, T> {
|
2022-10-26 16:47:29 +02:00
|
|
|
type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>> + 'a
|
2022-05-26 14:02:55 +03:00
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
|
2022-09-26 15:28:09 +02:00
|
|
|
self.inner_fill_buf()
|
|
|
|
}
|
2022-05-26 14:02:55 +03:00
|
|
|
|
2022-09-26 15:28:09 +02:00
|
|
|
fn consume(&mut self, amt: usize) {
|
|
|
|
self.inner_consume(amt)
|
|
|
|
}
|
|
|
|
}
|
2022-05-26 14:02:55 +03:00
|
|
|
|
2022-09-26 15:28:09 +02:00
|
|
|
impl<'u, 'd, T: BasicInstance> embedded_io::asynch::BufRead for BufferedUartRx<'u, 'd, T> {
|
2022-10-26 16:47:29 +02:00
|
|
|
type FillBufFuture<'a> = impl Future<Output = Result<&'a [u8], Self::Error>> + 'a
|
2022-09-26 15:28:09 +02:00
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn fill_buf<'a>(&'a mut self) -> Self::FillBufFuture<'a> {
|
|
|
|
self.inner.inner_fill_buf()
|
2022-05-26 14:02:55 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
fn consume(&mut self, amt: usize) {
|
2022-09-26 15:28:09 +02:00
|
|
|
self.inner.inner_consume(amt)
|
2022-05-26 14:02:55 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2022-06-09 15:17:03 +02:00
|
|
|
impl<'d, T: BasicInstance> embedded_io::asynch::Write for BufferedUart<'d, T> {
|
2022-10-26 16:47:29 +02:00
|
|
|
type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a
|
2022-05-04 20:48:37 +02:00
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
2022-09-26 15:28:09 +02:00
|
|
|
self.inner_write(buf)
|
|
|
|
}
|
2022-05-04 20:48:37 +02:00
|
|
|
|
2022-10-26 16:47:29 +02:00
|
|
|
type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a
|
2022-09-26 15:28:09 +02:00
|
|
|
where
|
|
|
|
Self: 'a;
|
2022-05-04 20:48:37 +02:00
|
|
|
|
2022-09-26 15:28:09 +02:00
|
|
|
fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
|
|
|
|
self.inner_flush()
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
impl<'u, 'd, T: BasicInstance> embedded_io::asynch::Write for BufferedUartTx<'u, 'd, T> {
|
2022-10-26 16:47:29 +02:00
|
|
|
type WriteFuture<'a> = impl Future<Output = Result<usize, Self::Error>> + 'a
|
2022-09-26 15:28:09 +02:00
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
|
|
self.inner.inner_write(buf)
|
2022-05-04 20:48:37 +02:00
|
|
|
}
|
|
|
|
|
2022-10-26 16:47:29 +02:00
|
|
|
type FlushFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a
|
2022-05-04 20:48:37 +02:00
|
|
|
where
|
|
|
|
Self: 'a;
|
|
|
|
|
|
|
|
fn flush<'a>(&'a mut self) -> Self::FlushFuture<'a> {
|
2022-09-26 15:28:09 +02:00
|
|
|
self.inner.inner_flush()
|
2022-05-04 20:48:37 +02:00
|
|
|
}
|
|
|
|
}
|