68 lines
2.5 KiB
Rust
68 lines
2.5 KiB
Rust
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use embedded_hal_async::spi::{Operation, SpiDevice};
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#[repr(u8)]
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pub enum RegisterBlock {
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Common = 0x00,
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Socket0 = 0x01,
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TxBuf = 0x02,
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RxBuf = 0x03,
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}
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pub enum W5500 {}
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impl super::Chip for W5500 {}
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impl super::sealed::Chip for W5500 {
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type Address = (RegisterBlock, u16);
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const COMMON_MODE: Self::Address = (RegisterBlock::Common, 0x00);
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const COMMON_MAC: Self::Address = (RegisterBlock::Common, 0x09);
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const COMMON_SOCKET_INTR: Self::Address = (RegisterBlock::Common, 0x18);
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const COMMON_PHY_CFG: Self::Address = (RegisterBlock::Common, 0x2E);
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const SOCKET_MODE: Self::Address = (RegisterBlock::Socket0, 0x00);
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const SOCKET_COMMAND: Self::Address = (RegisterBlock::Socket0, 0x01);
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const SOCKET_RXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1E);
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const SOCKET_TXBUF_SIZE: Self::Address = (RegisterBlock::Socket0, 0x1F);
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const SOCKET_TX_FREE_SIZE: Self::Address = (RegisterBlock::Socket0, 0x20);
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const SOCKET_TX_DATA_WRITE_PTR: Self::Address = (RegisterBlock::Socket0, 0x24);
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const SOCKET_RECVD_SIZE: Self::Address = (RegisterBlock::Socket0, 0x26);
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const SOCKET_RX_DATA_READ_PTR: Self::Address = (RegisterBlock::Socket0, 0x28);
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const SOCKET_INTR_MASK: Self::Address = (RegisterBlock::Socket0, 0x2C);
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const SOCKET_INTR: Self::Address = (RegisterBlock::Socket0, 0x02);
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fn rx_addr(addr: u16) -> Self::Address {
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(RegisterBlock::RxBuf, addr)
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}
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fn tx_addr(addr: u16) -> Self::Address {
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(RegisterBlock::TxBuf, addr)
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}
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async fn bus_read<SPI: SpiDevice>(
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spi: &mut SPI,
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address: Self::Address,
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data: &mut [u8],
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) -> Result<(), SPI::Error> {
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let address_phase = address.1.to_be_bytes();
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let control_phase = [(address.0 as u8) << 3];
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let operations = &mut [
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Operation::Write(&address_phase),
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Operation::Write(&control_phase),
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Operation::TransferInPlace(data),
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];
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spi.transaction(operations).await
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}
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async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
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let address_phase = address.1.to_be_bytes();
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let control_phase = [(address.0 as u8) << 3 | 0b0000_0100];
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let data_phase = data;
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let operations = &mut [
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Operation::Write(&address_phase[..]),
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Operation::Write(&control_phase),
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Operation::Write(&data_phase),
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];
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spi.transaction(operations).await
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}
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}
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