2022-03-09 01:34:35 +01:00
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use core::mem;
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2022-03-30 20:17:15 +02:00
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use crate::descriptor::DescriptorWriter;
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2022-04-06 04:04:11 +02:00
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use crate::driver::{self, EndpointError};
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2022-03-29 23:13:16 +02:00
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2022-03-09 01:34:35 +01:00
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use super::types::*;
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/// Control request type.
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#[repr(u8)]
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#[derive(Copy, Clone, Eq, PartialEq, Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum RequestType {
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/// Request is a USB standard request. Usually handled by
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/// [`UsbDevice`](crate::device::UsbDevice).
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Standard = 0,
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/// Request is intended for a USB class.
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Class = 1,
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/// Request is vendor-specific.
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Vendor = 2,
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/// Reserved.
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Reserved = 3,
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}
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/// Control request recipient.
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#[derive(Copy, Clone, Eq, PartialEq, Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Recipient {
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/// Request is intended for the entire device.
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Device = 0,
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/// Request is intended for an interface. Generally, the `index` field of the request specifies
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/// the interface number.
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Interface = 1,
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/// Request is intended for an endpoint. Generally, the `index` field of the request specifies
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/// the endpoint address.
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Endpoint = 2,
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/// None of the above.
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Other = 3,
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/// Reserved.
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Reserved = 4,
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}
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/// A control request read from a SETUP packet.
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#[derive(Copy, Clone, Eq, PartialEq, Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct Request {
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/// Direction of the request.
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pub direction: UsbDirection,
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/// Type of the request.
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pub request_type: RequestType,
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/// Recipient of the request.
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pub recipient: Recipient,
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/// Request code. The meaning of the value depends on the previous fields.
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pub request: u8,
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/// Request value. The meaning of the value depends on the previous fields.
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pub value: u16,
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/// Request index. The meaning of the value depends on the previous fields.
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pub index: u16,
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/// Length of the DATA stage. For control OUT transfers this is the exact length of the data the
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/// host sent. For control IN transfers this is the maximum length of data the device should
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/// return.
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pub length: u16,
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}
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impl Request {
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/// Standard USB control request Get Status
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pub const GET_STATUS: u8 = 0;
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/// Standard USB control request Clear Feature
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pub const CLEAR_FEATURE: u8 = 1;
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/// Standard USB control request Set Feature
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pub const SET_FEATURE: u8 = 3;
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/// Standard USB control request Set Address
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pub const SET_ADDRESS: u8 = 5;
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/// Standard USB control request Get Descriptor
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pub const GET_DESCRIPTOR: u8 = 6;
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/// Standard USB control request Set Descriptor
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pub const SET_DESCRIPTOR: u8 = 7;
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/// Standard USB control request Get Configuration
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pub const GET_CONFIGURATION: u8 = 8;
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/// Standard USB control request Set Configuration
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pub const SET_CONFIGURATION: u8 = 9;
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/// Standard USB control request Get Interface
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pub const GET_INTERFACE: u8 = 10;
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/// Standard USB control request Set Interface
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pub const SET_INTERFACE: u8 = 11;
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/// Standard USB control request Synch Frame
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pub const SYNCH_FRAME: u8 = 12;
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/// Standard USB feature Endpoint Halt for Set/Clear Feature
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pub const FEATURE_ENDPOINT_HALT: u16 = 0;
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/// Standard USB feature Device Remote Wakeup for Set/Clear Feature
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pub const FEATURE_DEVICE_REMOTE_WAKEUP: u16 = 1;
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2022-03-25 21:46:14 +01:00
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/// Parses a USB control request from a byte array.
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pub fn parse(buf: &[u8; 8]) -> Request {
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let rt = buf[0];
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let recipient = rt & 0b11111;
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Request {
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direction: rt.into(),
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request_type: unsafe { mem::transmute((rt >> 5) & 0b11) },
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recipient: if recipient <= 3 {
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unsafe { mem::transmute(recipient) }
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} else {
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Recipient::Reserved
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},
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request: buf[1],
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value: (buf[2] as u16) | ((buf[3] as u16) << 8),
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index: (buf[4] as u16) | ((buf[5] as u16) << 8),
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length: (buf[6] as u16) | ((buf[7] as u16) << 8),
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}
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}
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/// Gets the descriptor type and index from the value field of a GET_DESCRIPTOR request.
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pub fn descriptor_type_index(&self) -> (u8, u8) {
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((self.value >> 8) as u8, self.value as u8)
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}
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}
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2022-03-28 03:27:21 +02:00
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#[derive(Copy, Clone, Eq, PartialEq, Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2022-03-28 03:30:08 +02:00
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pub enum OutResponse {
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2022-03-28 03:27:21 +02:00
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Accepted,
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Rejected,
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}
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2022-03-28 03:34:24 +02:00
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#[derive(Copy, Clone, Eq, PartialEq, Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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2022-03-29 02:10:13 +02:00
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pub enum InResponse<'a> {
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Accepted(&'a [u8]),
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Rejected,
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}
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2022-03-28 03:37:29 +02:00
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/// Handler for control requests.
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///
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/// All methods are optional callbacks that will be called by
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/// [`UsbDevice::run()`](crate::UsbDevice::run)
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pub trait ControlHandler {
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/// Called after a USB reset after the bus reset sequence is complete.
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fn reset(&mut self) {}
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2022-04-16 04:47:27 +02:00
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fn set_alternate_setting(&mut self, alternate_setting: u8) {
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let _ = alternate_setting;
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}
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2022-03-28 03:27:21 +02:00
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/// Called when a control request is received with direction HostToDevice.
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///
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/// # Arguments
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///
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/// * `req` - The request from the SETUP packet.
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/// * `data` - The data from the request.
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fn control_out(&mut self, req: Request, data: &[u8]) -> OutResponse {
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let _ = (req, data);
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OutResponse::Rejected
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}
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/// Called when a control request is received with direction DeviceToHost.
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///
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/// You should write the response somewhere (usually to `buf`, but you may use another buffer
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/// owned by yourself, or a static buffer), then return `InResponse::Accepted(data)`.
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///
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/// # Arguments
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///
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/// * `req` - The request from the SETUP packet.
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2022-03-29 21:09:24 +02:00
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fn control_in<'a>(&'a mut self, req: Request, buf: &'a mut [u8]) -> InResponse<'a> {
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let _ = (req, buf);
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InResponse::Rejected
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}
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2022-03-29 23:13:16 +02:00
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2022-04-16 04:47:27 +02:00
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/// Called when a GET DESCRIPTOR control request is received on the interface.
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///
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/// You should write the response somewhere (usually to `buf`, but you may use another buffer
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/// owned by yourself, or a static buffer), then return `InResponse::Accepted(data)`.
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///
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/// # Arguments
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///
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/// * `req` - The request from the SETUP packet.
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fn get_descriptor<'a>(&'a mut self, req: Request, buf: &'a mut [u8]) -> InResponse<'a> {
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let _ = (req, buf);
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InResponse::Rejected
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}
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2022-03-28 03:27:21 +02:00
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}
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2022-03-30 20:17:15 +02:00
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/// Typestate representing a ControlPipe in the DATA IN stage
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub(crate) struct DataInStage {
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2022-04-06 03:02:13 +02:00
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pub(crate) length: usize,
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}
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/// Typestate representing a ControlPipe in the DATA OUT stage
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub(crate) struct DataOutStage {
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length: usize,
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}
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/// Typestate representing a ControlPipe in the STATUS stage
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub(crate) struct StatusStage {}
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub(crate) enum Setup {
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DataIn(Request, DataInStage),
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DataOut(Request, DataOutStage),
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}
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pub(crate) struct ControlPipe<C: driver::ControlPipe> {
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control: C,
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}
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impl<C: driver::ControlPipe> ControlPipe<C> {
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pub(crate) fn new(control: C) -> Self {
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ControlPipe { control }
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}
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pub(crate) async fn setup(&mut self) -> Setup {
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let req = self.control.setup().await;
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trace!("control request: {:02x}", req);
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2022-03-30 20:17:15 +02:00
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match (req.direction, req.length) {
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(UsbDirection::Out, n) => Setup::DataOut(
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req,
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DataOutStage {
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length: usize::from(n),
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},
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),
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(UsbDirection::In, n) => Setup::DataIn(
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req,
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DataInStage {
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length: usize::from(n),
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},
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),
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}
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}
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pub(crate) async fn data_out<'a>(
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&mut self,
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buf: &'a mut [u8],
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stage: DataOutStage,
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2022-04-06 04:04:11 +02:00
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) -> Result<(&'a [u8], StatusStage), EndpointError> {
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2022-03-30 20:17:15 +02:00
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if stage.length == 0 {
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Ok((&[], StatusStage {}))
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} else {
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let req_length = stage.length;
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let max_packet_size = self.control.max_packet_size();
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let mut total = 0;
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for chunk in buf.chunks_mut(max_packet_size) {
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let size = self.control.data_out(chunk).await?;
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total += size;
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if size < max_packet_size || total == req_length {
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break;
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}
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}
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2022-04-02 04:53:42 +02:00
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let res = &buf[0..total];
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#[cfg(feature = "defmt")]
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2022-04-15 18:45:52 +02:00
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trace!(" control out data: {:02x}", res);
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2022-04-02 04:53:42 +02:00
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#[cfg(not(feature = "defmt"))]
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2022-04-15 18:45:52 +02:00
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trace!(" control out data: {:02x?}", res);
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2022-04-02 04:53:42 +02:00
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Ok((res, StatusStage {}))
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}
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}
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pub(crate) async fn accept_in(&mut self, buf: &[u8], stage: DataInStage) {
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#[cfg(feature = "defmt")]
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2022-04-02 04:53:42 +02:00
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trace!(" control in accept {:02x}", buf);
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#[cfg(not(feature = "defmt"))]
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2022-04-02 04:53:42 +02:00
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trace!(" control in accept {:02x?}", buf);
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2022-03-30 20:17:15 +02:00
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let req_len = stage.length;
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let len = buf.len().min(req_len);
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let max_packet_size = self.control.max_packet_size();
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let need_zlp = len != req_len && (len % usize::from(max_packet_size)) == 0;
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let mut chunks = buf[0..len]
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.chunks(max_packet_size)
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.chain(need_zlp.then(|| -> &[u8] { &[] }));
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while let Some(chunk) = chunks.next() {
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2022-04-06 03:14:22 +02:00
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match self.control.data_in(chunk, chunks.size_hint().0 == 0).await {
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Ok(()) => {}
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Err(e) => {
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warn!("control accept_in failed: {:?}", e);
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return;
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}
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}
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2022-03-30 20:17:15 +02:00
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}
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}
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pub(crate) async fn accept_in_writer(
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&mut self,
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req: Request,
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stage: DataInStage,
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f: impl FnOnce(&mut DescriptorWriter),
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) {
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let mut buf = [0; 256];
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let mut w = DescriptorWriter::new(&mut buf);
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f(&mut w);
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let pos = w.position().min(usize::from(req.length));
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self.accept_in(&buf[..pos], stage).await
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}
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pub(crate) fn accept(&mut self, _: StatusStage) {
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trace!(" control accept");
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self.control.accept();
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}
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pub(crate) fn reject(&mut self) {
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trace!(" control reject");
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2022-03-30 20:17:15 +02:00
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self.control.reject();
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}
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}
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