2023-05-02 13:16:48 +02:00
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use core::mem::MaybeUninit;
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use bit_field::BitField;
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2023-05-26 10:56:55 +02:00
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use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
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2023-05-15 11:25:02 +02:00
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use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
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use embassy_sync::channel::Channel;
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2023-05-02 13:16:48 +02:00
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use self::ble::Ble;
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use self::cmd::{AclDataPacket, CmdPacket};
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2023-05-15 11:25:02 +02:00
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use self::evt::{CsEvt, EvtBox};
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2023-05-02 13:16:48 +02:00
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use self::mm::MemoryManager;
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2023-05-15 11:25:02 +02:00
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use self::shci::{shci_ble_init, ShciBleInitCmdParam};
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2023-05-02 13:16:48 +02:00
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use self::sys::Sys;
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use self::unsafe_linked_list::LinkedListNode;
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2023-05-25 00:29:56 +02:00
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use crate::interrupt;
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2023-05-26 10:56:55 +02:00
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use crate::ipcc::{Config, Ipcc};
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2023-05-02 13:16:48 +02:00
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2023-05-26 12:26:58 +02:00
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mod ble;
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2023-05-02 13:16:48 +02:00
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mod channels;
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mod cmd;
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2023-05-15 11:25:02 +02:00
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mod consts;
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2023-05-02 13:16:48 +02:00
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mod evt;
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mod mm;
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2023-05-15 11:25:02 +02:00
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mod shci;
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2023-05-02 13:16:48 +02:00
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mod sys;
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mod unsafe_linked_list;
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pub type PacketHeader = LinkedListNode;
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const TL_PACKET_HEADER_SIZE: usize = core::mem::size_of::<PacketHeader>();
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const TL_EVT_HEADER_SIZE: usize = 3;
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const TL_CS_EVT_SIZE: usize = core::mem::size_of::<CsEvt>();
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const CFG_TL_BLE_EVT_QUEUE_LENGTH: usize = 5;
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const CFG_TL_BLE_MOST_EVENT_PAYLOAD_SIZE: usize = 255;
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const TL_BLE_EVENT_FRAME_SIZE: usize = TL_EVT_HEADER_SIZE + CFG_TL_BLE_MOST_EVENT_PAYLOAD_SIZE;
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const POOL_SIZE: usize = CFG_TL_BLE_EVT_QUEUE_LENGTH * 4 * divc(TL_PACKET_HEADER_SIZE + TL_BLE_EVENT_FRAME_SIZE, 4);
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const fn divc(x: usize, y: usize) -> usize {
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(x + y - 1) / y
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}
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#[repr(C, packed)]
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#[derive(Copy, Clone)]
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pub struct SafeBootInfoTable {
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version: u32,
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}
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#[repr(C, packed)]
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#[derive(Copy, Clone)]
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2023-05-12 11:26:46 +02:00
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pub struct FusInfoTable {
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2023-05-02 13:16:48 +02:00
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version: u32,
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memory_size: u32,
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2023-05-12 11:26:46 +02:00
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fus_info: u32,
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2023-05-02 13:16:48 +02:00
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}
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2023-05-25 00:29:56 +02:00
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/// Interrupt handler.
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pub struct ReceiveInterruptHandler {}
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impl interrupt::Handler<interrupt::IPCC_C1_RX> for ReceiveInterruptHandler {
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2023-05-26 10:56:55 +02:00
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unsafe fn on_interrupt() {
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if Ipcc::is_rx_pending(channels::cpu2::IPCC_SYSTEM_EVENT_CHANNEL) {
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sys::Sys::evt_handler();
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} else if Ipcc::is_rx_pending(channels::cpu2::IPCC_BLE_EVENT_CHANNEL) {
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ble::Ble::evt_handler();
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} else {
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todo!()
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}
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}
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2023-05-25 00:29:56 +02:00
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}
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pub struct TransmitInterruptHandler {}
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impl interrupt::Handler<interrupt::IPCC_C1_TX> for TransmitInterruptHandler {
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2023-05-26 10:56:55 +02:00
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unsafe fn on_interrupt() {
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if Ipcc::is_tx_pending(channels::cpu1::IPCC_SYSTEM_CMD_RSP_CHANNEL) {
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// TODO: handle this case
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let _ = sys::Sys::cmd_evt_handler();
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} else if Ipcc::is_tx_pending(channels::cpu1::IPCC_MM_RELEASE_BUFFER_CHANNEL) {
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mm::MemoryManager::evt_handler();
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} else {
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todo!()
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}
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}
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2023-05-25 00:29:56 +02:00
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}
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2023-05-02 13:16:48 +02:00
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/// # Version
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/// - 0 -> 3 = Build - 0: Untracked - 15:Released - x: Tracked version
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/// - 4 -> 7 = branch - 0: Mass Market - x: ...
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/// - 8 -> 15 = Subversion
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/// - 16 -> 23 = Version minor
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/// - 24 -> 31 = Version major
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/// # Memory Size
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/// - 0 -> 7 = Flash ( Number of 4k sector)
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/// - 8 -> 15 = Reserved ( Shall be set to 0 - may be used as flash extension )
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/// - 16 -> 23 = SRAM2b ( Number of 1k sector)
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/// - 24 -> 31 = SRAM2a ( Number of 1k sector)
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#[repr(C, packed)]
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#[derive(Copy, Clone)]
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pub struct WirelessFwInfoTable {
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version: u32,
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memory_size: u32,
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info_stack: u32,
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reserved: u32,
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2023-05-02 13:16:48 +02:00
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}
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impl WirelessFwInfoTable {
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pub fn version_major(&self) -> u8 {
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let version = self.version;
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(version.get_bits(24..31) & 0xff) as u8
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}
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pub fn version_minor(&self) -> u8 {
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let version = self.version;
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(version.get_bits(16..23) & 0xff) as u8
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}
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pub fn subversion(&self) -> u8 {
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let version = self.version;
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(version.get_bits(8..15) & 0xff) as u8
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}
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/// size of FLASH, expressed in number of 4K sectors
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pub fn flash_size(&self) -> u8 {
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let memory_size = self.memory_size;
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(memory_size.get_bits(0..7) & 0xff) as u8
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}
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/// size for SRAM2a, expressed in number of 1K sectors
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pub fn sram2a_size(&self) -> u8 {
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let memory_size = self.memory_size;
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(memory_size.get_bits(24..31) & 0xff) as u8
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}
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/// size of SRAM2b, expressed in number of 1K sectors
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pub fn sram2b_size(&self) -> u8 {
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let memory_size = self.memory_size;
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(memory_size.get_bits(16..23) & 0xff) as u8
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}
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}
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#[repr(C, packed)]
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#[derive(Copy, Clone)]
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pub struct DeviceInfoTable {
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pub safe_boot_info_table: SafeBootInfoTable,
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pub fus_info_table: FusInfoTable,
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pub wireless_fw_info_table: WirelessFwInfoTable,
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}
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#[repr(C, packed)]
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struct BleTable {
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2023-05-03 12:11:51 +02:00
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pcmd_buffer: *mut CmdPacket,
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pcs_buffer: *const u8,
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pevt_queue: *const u8,
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phci_acl_data_buffer: *mut AclDataPacket,
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}
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#[repr(C, packed)]
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struct ThreadTable {
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no_stack_buffer: *const u8,
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cli_cmd_rsp_buffer: *const u8,
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ot_cmd_rsp_buffer: *const u8,
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}
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#[repr(C, packed)]
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struct SysTable {
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pcmd_buffer: *mut CmdPacket,
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sys_queue: *const LinkedListNode,
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}
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#[allow(dead_code)] // Not used currently but reserved
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#[repr(C, packed)]
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struct LldTestTable {
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cli_cmd_rsp_buffer: *const u8,
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m0_cmd_buffer: *const u8,
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}
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#[allow(dead_code)] // Not used currently but reserved
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#[repr(C, packed)]
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struct BleLldTable {
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cmd_rsp_buffer: *const u8,
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m0_cmd_buffer: *const u8,
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}
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#[allow(dead_code)] // Not used currently but reserved
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#[repr(C, packed)]
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struct ZigbeeTable {
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notif_m0_to_m4_buffer: *const u8,
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appli_cmd_m4_to_m0_buffer: *const u8,
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request_m0_to_m4_buffer: *const u8,
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}
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#[repr(C, packed)]
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struct MemManagerTable {
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spare_ble_buffer: *const u8,
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spare_sys_buffer: *const u8,
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ble_pool: *const u8,
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ble_pool_size: u32,
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pevt_free_buffer_queue: *mut LinkedListNode,
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traces_evt_pool: *const u8,
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traces_pool_size: u32,
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}
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#[repr(C, packed)]
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struct TracesTable {
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traces_queue: *const u8,
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}
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#[repr(C, packed)]
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struct Mac802_15_4Table {
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2023-05-26 12:26:58 +02:00
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pcmd_rsp_buffer: *const u8,
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pnotack_buffer: *const u8,
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2023-05-02 13:16:48 +02:00
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evt_queue: *const u8,
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}
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/// reference table. Contains pointers to all other tables
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#[repr(C, packed)]
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#[derive(Copy, Clone)]
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pub struct RefTable {
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pub device_info_table: *const DeviceInfoTable,
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ble_table: *const BleTable,
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thread_table: *const ThreadTable,
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sys_table: *const SysTable,
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mem_manager_table: *const MemManagerTable,
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traces_table: *const TracesTable,
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mac_802_15_4_table: *const Mac802_15_4Table,
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2023-05-12 11:26:46 +02:00
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zigbee_table: *const ZigbeeTable,
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lld_tests_table: *const LldTestTable,
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ble_lld_table: *const BleLldTable,
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2023-05-02 13:16:48 +02:00
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}
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#[link_section = "TL_REF_TABLE"]
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pub static mut TL_REF_TABLE: MaybeUninit<RefTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_DEVICE_INFO_TABLE: MaybeUninit<DeviceInfoTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_BLE_TABLE: MaybeUninit<BleTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_THREAD_TABLE: MaybeUninit<ThreadTable> = MaybeUninit::uninit();
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2023-05-12 11:26:46 +02:00
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#[link_section = "MB_MEM1"]
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static mut TL_LLD_TESTS_TABLE: MaybeUninit<LldTestTable> = MaybeUninit::uninit();
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#[link_section = "MB_MEM1"]
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static mut TL_BLE_LLD_TABLE: MaybeUninit<BleLldTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_SYS_TABLE: MaybeUninit<SysTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_MEM_MANAGER_TABLE: MaybeUninit<MemManagerTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_TRACES_TABLE: MaybeUninit<TracesTable> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut TL_MAC_802_15_4_TABLE: MaybeUninit<Mac802_15_4Table> = MaybeUninit::uninit();
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2023-05-12 11:26:46 +02:00
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#[link_section = "MB_MEM1"]
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static mut TL_ZIGBEE_TABLE: MaybeUninit<ZigbeeTable> = MaybeUninit::uninit();
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2023-05-26 12:26:58 +02:00
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#[allow(dead_code)] // Not used currently but reserved
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2023-05-12 11:26:46 +02:00
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#[link_section = "MB_MEM1"]
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2023-05-02 13:16:48 +02:00
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static mut FREE_BUFF_QUEUE: MaybeUninit<LinkedListNode> = MaybeUninit::uninit();
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2023-05-26 12:26:58 +02:00
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// not in shared RAM
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static mut LOCAL_FREE_BUF_QUEUE: MaybeUninit<LinkedListNode> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-02 13:16:48 +02:00
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static mut CS_BUFFER: MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + TL_CS_EVT_SIZE]> =
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MaybeUninit::uninit();
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2023-05-26 12:26:58 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-02 13:16:48 +02:00
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static mut EVT_QUEUE: MaybeUninit<LinkedListNode> = MaybeUninit::uninit();
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2023-05-15 11:25:02 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-02 13:16:48 +02:00
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static mut SYSTEM_EVT_QUEUE: MaybeUninit<LinkedListNode> = MaybeUninit::uninit();
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2023-05-25 17:39:43 +02:00
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#[link_section = "MB_MEM2"]
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static mut SYS_CMD_BUF: MaybeUninit<CmdPacket> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-26 12:26:58 +02:00
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static mut EVT_POOL: MaybeUninit<[u8; POOL_SIZE]> = MaybeUninit::uninit();
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2023-05-25 17:39:43 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-26 12:26:58 +02:00
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static mut SYS_SPARE_EVT_BUF: MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]> =
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2023-05-02 13:16:48 +02:00
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MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-25 17:39:43 +02:00
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static mut BLE_SPARE_EVT_BUF: MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + TL_EVT_HEADER_SIZE + 255]> =
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MaybeUninit::uninit();
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2023-05-26 12:26:58 +02:00
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#[link_section = "MB_MEM2"]
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2023-05-02 13:16:48 +02:00
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static mut BLE_CMD_BUFFER: MaybeUninit<CmdPacket> = MaybeUninit::uninit();
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2023-05-04 12:02:17 +02:00
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#[link_section = "MB_MEM2"]
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// "magic" numbers from ST ---v---v
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2023-05-02 13:16:48 +02:00
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static mut HCI_ACL_DATA_BUFFER: MaybeUninit<[u8; TL_PACKET_HEADER_SIZE + 5 + 251]> = MaybeUninit::uninit();
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2023-05-15 11:25:02 +02:00
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// TODO: get a better size, this is a placeholder
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pub(crate) static TL_CHANNEL: Channel<CriticalSectionRawMutex, EvtBox, 5> = Channel::new();
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2023-05-26 12:26:58 +02:00
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pub struct TlMbox {
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_sys: Sys,
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_ble: Ble,
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_mm: MemoryManager,
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2023-05-02 13:16:48 +02:00
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}
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impl TlMbox {
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/// initializes low-level transport between CPU1 and BLE stack on CPU2
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2023-05-25 00:29:56 +02:00
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pub fn init(
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_irqs: impl interrupt::Binding<interrupt::IPCC_C1_RX, ReceiveInterruptHandler>
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+ interrupt::Binding<interrupt::IPCC_C1_TX, TransmitInterruptHandler>,
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2023-05-26 10:56:55 +02:00
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config: Config,
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2023-05-25 00:29:56 +02:00
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) -> TlMbox {
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2023-05-02 13:16:48 +02:00
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unsafe {
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TL_REF_TABLE = MaybeUninit::new(RefTable {
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device_info_table: TL_DEVICE_INFO_TABLE.as_ptr(),
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ble_table: TL_BLE_TABLE.as_ptr(),
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thread_table: TL_THREAD_TABLE.as_ptr(),
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sys_table: TL_SYS_TABLE.as_ptr(),
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mem_manager_table: TL_MEM_MANAGER_TABLE.as_ptr(),
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traces_table: TL_TRACES_TABLE.as_ptr(),
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mac_802_15_4_table: TL_MAC_802_15_4_TABLE.as_ptr(),
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2023-05-12 11:26:46 +02:00
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zigbee_table: TL_ZIGBEE_TABLE.as_ptr(),
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lld_tests_table: TL_LLD_TESTS_TABLE.as_ptr(),
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ble_lld_table: TL_BLE_LLD_TABLE.as_ptr(),
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2023-05-02 13:16:48 +02:00
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});
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TL_SYS_TABLE = MaybeUninit::zeroed();
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TL_DEVICE_INFO_TABLE = MaybeUninit::zeroed();
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TL_BLE_TABLE = MaybeUninit::zeroed();
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TL_THREAD_TABLE = MaybeUninit::zeroed();
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TL_MEM_MANAGER_TABLE = MaybeUninit::zeroed();
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TL_TRACES_TABLE = MaybeUninit::zeroed();
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TL_MAC_802_15_4_TABLE = MaybeUninit::zeroed();
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2023-05-12 11:26:46 +02:00
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TL_ZIGBEE_TABLE = MaybeUninit::zeroed();
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TL_LLD_TESTS_TABLE = MaybeUninit::zeroed();
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TL_BLE_LLD_TABLE = MaybeUninit::zeroed();
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2023-05-02 13:16:48 +02:00
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EVT_POOL = MaybeUninit::zeroed();
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SYS_SPARE_EVT_BUF = MaybeUninit::zeroed();
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BLE_SPARE_EVT_BUF = MaybeUninit::zeroed();
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CS_BUFFER = MaybeUninit::zeroed();
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BLE_CMD_BUFFER = MaybeUninit::zeroed();
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HCI_ACL_DATA_BUFFER = MaybeUninit::zeroed();
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}
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2023-05-26 10:56:55 +02:00
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Ipcc::init(config);
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2023-05-02 13:16:48 +02:00
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2023-05-26 12:26:58 +02:00
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let _sys = Sys::new();
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let _ble = Ble::new();
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let _mm = MemoryManager::new();
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2023-05-02 13:16:48 +02:00
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2023-05-26 10:56:55 +02:00
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// enable interrupts
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unsafe { crate::interrupt::IPCC_C1_RX::steal() }.unpend();
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unsafe { crate::interrupt::IPCC_C1_TX::steal() }.unpend();
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unsafe { crate::interrupt::IPCC_C1_RX::steal() }.enable();
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unsafe { crate::interrupt::IPCC_C1_TX::steal() }.enable();
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2023-05-15 11:25:02 +02:00
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2023-05-26 12:26:58 +02:00
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TlMbox { _sys, _ble, _mm }
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2023-05-02 13:16:48 +02:00
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}
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pub fn wireless_fw_info(&self) -> Option<WirelessFwInfoTable> {
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let info = unsafe { &(*(*TL_REF_TABLE.as_ptr()).device_info_table).wireless_fw_info_table };
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// zero version indicates that CPU2 wasn't active and didn't fill the information table
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if info.version != 0 {
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Some(*info)
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} else {
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None
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}
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}
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2023-05-15 11:25:02 +02:00
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2023-05-26 10:56:55 +02:00
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pub fn shci_ble_init(&self, param: ShciBleInitCmdParam) {
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shci_ble_init(param);
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2023-05-15 11:25:02 +02:00
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}
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2023-05-26 12:26:58 +02:00
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pub fn send_ble_cmd(&self, buf: &[u8]) {
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ble::Ble::send_cmd(buf);
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2023-05-15 11:25:02 +02:00
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}
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2023-05-26 12:26:58 +02:00
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// pub fn send_sys_cmd(&self, buf: &[u8]) {
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// sys::Sys::send_cmd(buf);
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// }
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2023-05-15 11:25:02 +02:00
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pub async fn read(&self) -> EvtBox {
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TL_CHANNEL.recv().await
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}
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2023-05-02 13:16:48 +02:00
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}
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