embassy/embassy-nrf/src/lib.rs

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#![no_std]
#![feature(generic_associated_types)]
#![feature(asm)]
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#![feature(min_type_alias_impl_trait)]
#![feature(impl_trait_in_bindings)]
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#![feature(type_alias_impl_trait)]
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#![allow(incomplete_features)]
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#[cfg(not(any(
feature = "52810",
feature = "52811",
feature = "52832",
feature = "52833",
feature = "52840",
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)))]
compile_error!("No chip feature activated. You must activate exactly one of the following features: 52810, 52811, 52832, 52833, 52840");
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#[cfg(any(
all(feature = "52810", feature = "52811"),
all(feature = "52810", feature = "52832"),
all(feature = "52810", feature = "52833"),
all(feature = "52810", feature = "52840"),
all(feature = "52811", feature = "52832"),
all(feature = "52811", feature = "52833"),
all(feature = "52811", feature = "52840"),
all(feature = "52832", feature = "52833"),
all(feature = "52832", feature = "52840"),
all(feature = "52833", feature = "52840"),
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))]
compile_error!("Multile chip features activated. You must activate exactly one of the following features: 52810, 52811, 52832, 52833, 52840");
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#[cfg(feature = "52810")]
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pub use nrf52810_pac as pac;
#[cfg(feature = "52811")]
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pub use nrf52811_pac as pac;
#[cfg(feature = "52832")]
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pub use nrf52832_pac as pac;
#[cfg(feature = "52833")]
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pub use nrf52833_pac as pac;
#[cfg(feature = "52840")]
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pub use nrf52840_pac as pac;
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/// Length of Nordic EasyDMA differs for MCUs
#[cfg(any(
feature = "52810",
feature = "52811",
feature = "52832",
feature = "51"
))]
pub mod target_constants {
// NRF52832 8 bits1..0xFF
pub const EASY_DMA_SIZE: usize = 255;
// Easy DMA can only read from data ram
pub const SRAM_LOWER: usize = 0x2000_0000;
pub const SRAM_UPPER: usize = 0x3000_0000;
}
#[cfg(any(feature = "52840", feature = "52833", feature = "9160"))]
pub mod target_constants {
// NRF52840 and NRF9160 16 bits 1..0xFFFF
pub const EASY_DMA_SIZE: usize = 65535;
// Limits for Easy DMA - it can only read from data ram
pub const SRAM_LOWER: usize = 0x2000_0000;
pub const SRAM_UPPER: usize = 0x3000_0000;
}
/// Does this slice reside entirely within RAM?
pub(crate) fn slice_in_ram(slice: &[u8]) -> bool {
let ptr = slice.as_ptr() as usize;
ptr >= target_constants::SRAM_LOWER && (ptr + slice.len()) < target_constants::SRAM_UPPER
}
/// Return an error if slice is not in RAM.
#[cfg(not(feature = "51"))]
pub(crate) fn slice_in_ram_or<T>(slice: &[u8], err: T) -> Result<(), T> {
if slice.len() == 0 || slice_in_ram(slice) {
Ok(())
} else {
Err(err)
}
}
// This mod MUST go first, so that the others see its macros.
pub(crate) mod fmt;
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pub mod buffered_uarte;
pub mod gpio;
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pub mod gpiote;
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pub mod interrupt;
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pub mod ppi;
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#[cfg(feature = "52840")]
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pub mod qspi;
pub mod rtc;
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pub mod saadc;
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pub mod spim;
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pub mod system;
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pub mod timer;
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pub mod uarte;
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embassy_extras::peripherals! {
// RTC
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RTC0,
RTC1,
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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RTC2,
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// QSPI
#[cfg(feature = "52840")]
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QSPI,
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// UARTE
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UARTE0,
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#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
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UARTE1,
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// SPIM
// TODO this is actually shared with SPI, SPIM, SPIS, TWI, TWIS, TWIS.
// When they're all implemented, they should be only one peripheral here.
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SPIM0,
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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SPIM1,
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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SPIM2,
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#[cfg(any(feature = "52833", feature = "52840"))]
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SPIM3,
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// SAADC
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SAADC,
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// TIMER
TIMER0,
TIMER1,
TIMER2,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
TIMER3,
#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
TIMER4,
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// GPIOTE
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GPIOTE,
GPIOTE_CH0,
GPIOTE_CH1,
GPIOTE_CH2,
GPIOTE_CH3,
GPIOTE_CH4,
GPIOTE_CH5,
GPIOTE_CH6,
GPIOTE_CH7,
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// PPI
PPI_CH0,
PPI_CH1,
PPI_CH2,
PPI_CH3,
PPI_CH4,
PPI_CH5,
PPI_CH6,
PPI_CH7,
PPI_CH8,
PPI_CH9,
PPI_CH10,
PPI_CH11,
PPI_CH12,
PPI_CH13,
PPI_CH14,
PPI_CH15,
#[cfg(not(feature = "51"))]
PPI_CH16,
#[cfg(not(feature = "51"))]
PPI_CH17,
#[cfg(not(feature = "51"))]
PPI_CH18,
#[cfg(not(feature = "51"))]
PPI_CH19,
PPI_CH20,
PPI_CH21,
PPI_CH22,
PPI_CH23,
PPI_CH24,
PPI_CH25,
PPI_CH26,
PPI_CH27,
PPI_CH28,
PPI_CH29,
PPI_CH30,
PPI_CH31,
PPI_GROUP0,
PPI_GROUP1,
PPI_GROUP2,
PPI_GROUP3,
#[cfg(not(feature = "51"))]
PPI_GROUP4,
#[cfg(not(feature = "51"))]
PPI_GROUP5,
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// GPIO port 0
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P0_00,
P0_01,
P0_02,
P0_03,
P0_04,
P0_05,
P0_06,
P0_07,
P0_08,
P0_09,
P0_10,
P0_11,
P0_12,
P0_13,
P0_14,
P0_15,
P0_16,
P0_17,
P0_18,
P0_19,
P0_20,
P0_21,
P0_22,
P0_23,
P0_24,
P0_25,
P0_26,
P0_27,
P0_28,
P0_29,
P0_30,
P0_31,
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// GPIO port 1
#[cfg(any(feature = "52833", feature = "52840"))]
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P1_00,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_01,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_02,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_03,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_04,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_05,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_06,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_07,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_08,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_09,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_10,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_11,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_12,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_13,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_14,
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#[cfg(any(feature = "52833", feature = "52840"))]
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P1_15,
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}