311 lines
9.5 KiB
Rust
311 lines
9.5 KiB
Rust
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use embassy_hal_common::into_ref;
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::AnyPin;
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use crate::pac::spi::vals;
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use crate::rcc::get_freqs;
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use crate::spi::{Config as SpiConfig, *};
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use crate::time::Hertz;
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use crate::{Peripheral, PeripheralRef};
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#[derive(Copy, Clone)]
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pub enum Mode {
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Master,
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Slave,
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}
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#[derive(Copy, Clone)]
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pub enum Function {
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Transmit,
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Receive,
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}
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#[derive(Copy, Clone)]
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pub enum Standard {
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Philips,
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MsbFirst,
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LsbFirst,
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PcmLongSync,
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PcmShortSync,
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}
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impl Standard {
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#[cfg(any(spi_v1, spi_f1))]
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pub const fn i2sstd(&self) -> vals::I2sstd {
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match self {
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Standard::Philips => vals::I2sstd::PHILIPS,
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Standard::MsbFirst => vals::I2sstd::MSB,
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Standard::LsbFirst => vals::I2sstd::LSB,
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Standard::PcmLongSync => vals::I2sstd::PCM,
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Standard::PcmShortSync => vals::I2sstd::PCM,
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}
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}
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#[cfg(any(spi_v1, spi_f1))]
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pub const fn pcmsync(&self) -> vals::Pcmsync {
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match self {
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Standard::PcmLongSync => vals::Pcmsync::LONG,
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_ => vals::Pcmsync::SHORT,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum Format {
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/// 16 bit data length on 16 bit wide channel
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Data16Channel16,
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/// 16 bit data length on 32 bit wide channel
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Data16Channel32,
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/// 24 bit data length on 32 bit wide channel
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Data24Channel32,
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/// 32 bit data length on 32 bit wide channel
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Data32Channel32,
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}
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impl Format {
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#[cfg(any(spi_v1, spi_f1))]
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pub const fn datlen(&self) -> vals::Datlen {
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match self {
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Format::Data16Channel16 => vals::Datlen::SIXTEENBIT,
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Format::Data16Channel32 => vals::Datlen::SIXTEENBIT,
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Format::Data24Channel32 => vals::Datlen::TWENTYFOURBIT,
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Format::Data32Channel32 => vals::Datlen::THIRTYTWOBIT,
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}
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}
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#[cfg(any(spi_v1, spi_f1))]
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pub const fn chlen(&self) -> vals::Chlen {
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match self {
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Format::Data16Channel16 => vals::Chlen::SIXTEENBIT,
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Format::Data16Channel32 => vals::Chlen::THIRTYTWOBIT,
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Format::Data24Channel32 => vals::Chlen::THIRTYTWOBIT,
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Format::Data32Channel32 => vals::Chlen::THIRTYTWOBIT,
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}
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}
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}
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#[derive(Copy, Clone)]
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pub enum ClockPolarity {
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IdleLow,
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IdleHigh,
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}
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impl ClockPolarity {
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#[cfg(any(spi_v1, spi_f1))]
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pub const fn ckpol(&self) -> vals::Ckpol {
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match self {
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ClockPolarity::IdleHigh => vals::Ckpol::IDLEHIGH,
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ClockPolarity::IdleLow => vals::Ckpol::IDLELOW,
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}
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}
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}
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/// [`I2S`] configuration.
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///
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/// - `MS`: `Master` or `Slave`
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/// - `TR`: `Transmit` or `Receive`
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/// - `STD`: I2S standard, eg `Philips`
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/// - `FMT`: Frame Format marker, eg `Data16Channel16`
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#[non_exhaustive]
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#[derive(Copy, Clone)]
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pub struct Config {
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pub mode: Mode,
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pub function: Function,
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pub standard: Standard,
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pub format: Format,
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pub clock_polarity: ClockPolarity,
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pub master_clock: bool,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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mode: Mode::Master,
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function: Function::Transmit,
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standard: Standard::Philips,
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format: Format::Data16Channel16,
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clock_polarity: ClockPolarity::IdleLow,
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master_clock: true,
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}
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}
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}
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pub struct I2S<'d, T: Instance, Tx, Rx> {
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_peri: Spi<'d, T, Tx, Rx>,
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sd: Option<PeripheralRef<'d, AnyPin>>,
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ws: Option<PeripheralRef<'d, AnyPin>>,
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ck: Option<PeripheralRef<'d, AnyPin>>,
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mck: Option<PeripheralRef<'d, AnyPin>>,
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}
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impl<'d, T: Instance, Tx, Rx> I2S<'d, T, Tx, Rx> {
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/// Note: Full-Duplex modes are not supported at this time
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pub fn new(
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peri: impl Peripheral<P = T> + 'd,
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sd: impl Peripheral<P = impl MosiPin<T>> + 'd,
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ws: impl Peripheral<P = impl WsPin<T>> + 'd,
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ck: impl Peripheral<P = impl CkPin<T>> + 'd,
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mck: impl Peripheral<P = impl MckPin<T>> + 'd,
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txdma: impl Peripheral<P = Tx> + 'd,
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rxdma: impl Peripheral<P = Rx> + 'd,
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(sd, ws, ck, mck);
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unsafe {
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sd.set_as_af(sd.af_num(), AFType::OutputPushPull);
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sd.set_speed(crate::gpio::Speed::VeryHigh);
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ws.set_as_af(ws.af_num(), AFType::OutputPushPull);
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ws.set_speed(crate::gpio::Speed::VeryHigh);
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ck.set_as_af(ck.af_num(), AFType::OutputPushPull);
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ck.set_speed(crate::gpio::Speed::VeryHigh);
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mck.set_as_af(mck.af_num(), AFType::OutputPushPull);
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mck.set_speed(crate::gpio::Speed::VeryHigh);
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}
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let spi = Spi::new_internal(peri, txdma, rxdma, freq, SpiConfig::default());
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#[cfg(all(rcc_f4, not(stm32f410)))]
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let pclk = unsafe { get_freqs() }.plli2s.unwrap();
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#[cfg(stm32f410)]
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let pclk = T::frequency();
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let (odd, div) = compute_baud_rate(pclk, freq, config.master_clock, config.format);
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#[cfg(any(spi_v1, spi_f1))]
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unsafe {
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use stm32_metapac::spi::vals::{I2scfg, Odd};
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// 1. Select the I2SDIV[7:0] bits in the SPI_I2SPR register to define the serial clock baud
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// rate to reach the proper audio sample frequency. The ODD bit in the SPI_I2SPR
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// register also has to be defined.
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T::REGS.i2spr().modify(|w| {
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w.set_i2sdiv(div);
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w.set_odd(match odd {
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true => Odd::ODD,
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false => Odd::EVEN,
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});
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w.set_mckoe(config.master_clock);
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});
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// 2. Select the CKPOL bit to define the steady level for the communication clock. Set the
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// MCKOE bit in the SPI_I2SPR register if the master clock MCK needs to be provided to
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// the external DAC/ADC audio component (the I2SDIV and ODD values should be
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// computed depending on the state of the MCK output, for more details refer to
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// Section 28.4.4: Clock generator).
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// 3. Set the I2SMOD bit in SPI_I2SCFGR to activate the I2S functionalities and choose the
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// I2S standard through the I2SSTD[1:0] and PCMSYNC bits, the data length through the
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// DATLEN[1:0] bits and the number of bits per channel by configuring the CHLEN bit.
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// Select also the I2S master mode and direction (Transmitter or Receiver) through the
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// I2SCFG[1:0] bits in the SPI_I2SCFGR register.
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// 4. If needed, select all the potential interruption sources and the DMA capabilities by
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// writing the SPI_CR2 register.
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// 5. The I2SE bit in SPI_I2SCFGR register must be set.
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T::REGS.i2scfgr().modify(|w| {
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w.set_ckpol(config.clock_polarity.ckpol());
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w.set_i2smod(true);
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w.set_i2sstd(config.standard.i2sstd());
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w.set_pcmsync(config.standard.pcmsync());
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w.set_datlen(config.format.datlen());
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w.set_chlen(config.format.chlen());
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w.set_i2scfg(match (config.mode, config.function) {
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(Mode::Master, Function::Transmit) => I2scfg::MASTERTX,
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(Mode::Master, Function::Receive) => I2scfg::MASTERRX,
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(Mode::Slave, Function::Transmit) => I2scfg::SLAVETX,
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(Mode::Slave, Function::Receive) => I2scfg::SLAVERX,
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});
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w.set_i2se(true)
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});
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}
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#[cfg(spi_v2)]
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unsafe {}
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#[cfg(any(spi_v3, spi_v4))]
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unsafe {}
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Self {
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_peri: spi,
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sd: Some(sd.map_into()),
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ws: Some(ws.map_into()),
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ck: Some(ck.map_into()),
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mck: Some(mck.map_into()),
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}
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}
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pub async fn write<W: Word>(&mut self, data: &[W]) -> Result<(), Error>
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where
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Tx: TxDma<T>,
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{
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self._peri.write(data).await
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}
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pub async fn read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error>
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where
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Tx: TxDma<T>,
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Rx: RxDma<T>,
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{
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self._peri.read(data).await
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}
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}
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impl<'d, T: Instance, Tx, Rx> Drop for I2S<'d, T, Tx, Rx> {
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fn drop(&mut self) {
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unsafe {
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self.sd.as_ref().map(|x| x.set_as_disconnected());
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self.ws.as_ref().map(|x| x.set_as_disconnected());
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self.ck.as_ref().map(|x| x.set_as_disconnected());
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self.mck.as_ref().map(|x| x.set_as_disconnected());
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}
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}
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}
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// Note, calculation details:
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// Fs = i2s_clock / [256 * ((2 * div) + odd)] when master clock is enabled
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// Fs = i2s_clock / [(channel_length * 2) * ((2 * div) + odd)]` when master clock is disabled
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// channel_length is 16 or 32
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//
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// can be rewritten as
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// Fs = i2s_clock / (coef * division)
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// where coef is a constant equal to 256, 64 or 32 depending channel length and master clock
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// and where division = (2 * div) + odd
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//
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// Equation can be rewritten as
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// division = i2s_clock/ (coef * Fs)
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//
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// note: division = (2 * div) + odd = (div << 1) + odd
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// in other word, from bits point of view, division[8:1] = div[7:0] and division[0] = odd
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fn compute_baud_rate(i2s_clock: Hertz, request_freq: Hertz, mclk: bool, data_format: Format) -> (bool, u8) {
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let coef = if mclk {
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256
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} else if let Format::Data16Channel16 = data_format {
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32
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} else {
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64
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};
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let (n, d) = (i2s_clock.0, coef * request_freq.0);
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let division = (n + (d >> 1)) / d;
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if division < 4 {
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(false, 2)
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} else if division > 511 {
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(true, 255)
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} else {
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((division & 1) == 1, (division >> 1) as u8)
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}
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}
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