162 lines
5.1 KiB
Rust
162 lines
5.1 KiB
Rust
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use crate::socket;
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use crate::spi::SpiInterface;
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use embedded_hal_async::spi::SpiDevice;
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pub const MODE: u16 = 0x00;
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pub const MAC: u16 = 0x09;
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pub const SOCKET_INTR: u16 = 0x18;
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pub const PHY_CFG: u16 = 0x2E;
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#[repr(u8)]
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pub enum RegisterBlock {
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Common = 0x00,
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Socket0 = 0x01,
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TxBuf = 0x02,
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RxBuf = 0x03,
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}
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/// W5500 in MACRAW mode
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct W5500<SPI> {
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bus: SpiInterface<SPI>,
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}
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impl<SPI: SpiDevice> W5500<SPI> {
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/// Create and initialize the W5500 driver
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pub async fn new(spi: SPI, mac_addr: [u8; 6]) -> Result<W5500<SPI>, SPI::Error> {
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let mut bus = SpiInterface(spi);
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// Reset device
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bus.write_frame(RegisterBlock::Common, MODE, &[0x80])
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.await?;
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// Enable interrupt pin
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bus.write_frame(RegisterBlock::Common, SOCKET_INTR, &[0x01])
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.await?;
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// Enable receive interrupt
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bus.write_frame(
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RegisterBlock::Socket0,
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socket::SOCKET_INTR_MASK,
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&[socket::Interrupt::Receive as u8],
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)
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.await?;
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// Set MAC address
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bus.write_frame(RegisterBlock::Common, MAC, &mac_addr)
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.await?;
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// Set the raw socket RX/TX buffer sizes to 16KB
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bus.write_frame(RegisterBlock::Socket0, socket::TXBUF_SIZE, &[16])
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.await?;
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bus.write_frame(RegisterBlock::Socket0, socket::RXBUF_SIZE, &[16])
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.await?;
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// MACRAW mode with MAC filtering.
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let mode: u8 = (1 << 2) | (1 << 7);
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bus.write_frame(RegisterBlock::Socket0, socket::MODE, &[mode])
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.await?;
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socket::command(&mut bus, socket::Command::Open).await?;
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Ok(Self { bus })
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}
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/// Read bytes from the RX buffer. Returns the number of bytes read.
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async fn read_bytes(&mut self, buffer: &mut [u8], offset: u16) -> Result<usize, SPI::Error> {
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let rx_size = socket::get_rx_size(&mut self.bus).await? as usize;
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let read_buffer = if rx_size > buffer.len() + offset as usize {
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buffer
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} else {
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&mut buffer[..rx_size - offset as usize]
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};
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let read_ptr = socket::get_rx_read_ptr(&mut self.bus)
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.await?
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.wrapping_add(offset);
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self.bus
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.read_frame(RegisterBlock::RxBuf, read_ptr, read_buffer)
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.await?;
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socket::set_rx_read_ptr(
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&mut self.bus,
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read_ptr.wrapping_add(read_buffer.len() as u16),
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)
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.await?;
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Ok(read_buffer.len())
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}
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/// Read an ethernet frame from the device. Returns the number of bytes read.
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pub async fn read_frame(&mut self, frame: &mut [u8]) -> Result<usize, SPI::Error> {
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let rx_size = socket::get_rx_size(&mut self.bus).await? as usize;
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if rx_size == 0 {
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return Ok(0);
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}
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socket::reset_interrupt(&mut self.bus, socket::Interrupt::Receive).await?;
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// First two bytes gives the size of the received ethernet frame
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let expected_frame_size: usize = {
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let mut frame_bytes = [0u8; 2];
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assert!(self.read_bytes(&mut frame_bytes[..], 0).await? == 2);
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u16::from_be_bytes(frame_bytes) as usize - 2
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};
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// Read the ethernet frame
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let read_buffer = if frame.len() > expected_frame_size {
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&mut frame[..expected_frame_size]
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} else {
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frame
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};
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let recvd_frame_size = self.read_bytes(read_buffer, 2).await?;
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// Register RX as completed
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socket::command(&mut self.bus, socket::Command::Receive).await?;
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// If the whole frame wasn't read, drop it
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if recvd_frame_size < expected_frame_size {
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Ok(0)
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} else {
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Ok(recvd_frame_size)
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}
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}
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/// Write an ethernet frame to the device. Returns number of bytes written
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pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
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let max_size = socket::get_tx_free_size(&mut self.bus).await? as usize;
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let write_data = if frame.len() < max_size {
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frame
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} else {
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&frame[..max_size]
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};
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let write_ptr = socket::get_tx_write_ptr(&mut self.bus).await?;
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self.bus
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.write_frame(RegisterBlock::TxBuf, write_ptr, write_data)
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.await?;
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socket::set_tx_write_ptr(
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&mut self.bus,
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write_ptr.wrapping_add(write_data.len() as u16),
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)
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.await?;
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socket::reset_interrupt(&mut self.bus, socket::Interrupt::SendOk).await?;
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socket::command(&mut self.bus, socket::Command::Send).await?;
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// Wait for TX to complete
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while !socket::is_interrupt(&mut self.bus, socket::Interrupt::SendOk).await? {}
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socket::reset_interrupt(&mut self.bus, socket::Interrupt::SendOk).await?;
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Ok(write_data.len())
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}
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pub async fn is_link_up(&mut self) -> bool {
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let mut link = [0];
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self.bus
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.read_frame(RegisterBlock::Common, PHY_CFG, &mut link)
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.await
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.ok();
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link[0] & 1 == 1
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}
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}
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