2021-08-31 14:32:48 +02:00
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/// Bit synchronization.
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///
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/// This must be cleared to `0x00` (the reset value) when using packet types
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/// other than LoRa.
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///
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/// Argument of [`set_bit_sync`](crate::subghz::SubGhz::set_bit_sync).
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#[derive(Debug, PartialEq, Eq, Clone, Copy)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct BitSync {
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val: u8,
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}
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impl BitSync {
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/// Bit synchronization register reset value.
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pub const RESET: BitSync = BitSync { val: 0x00 };
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/// Create a new [`BitSync`] structure from a raw value.
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///
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/// Reserved bits will be masked.
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pub const fn from_raw(raw: u8) -> Self {
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Self { val: raw & 0x70 }
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}
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/// Get the raw value of the [`BitSync`] register.
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pub const fn as_bits(&self) -> u8 {
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self.val
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}
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/// LoRa simple bit synchronization enable.
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///
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/// # Example
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///
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/// Enable simple bit synchronization.
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///
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/// ```
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2022-06-14 16:22:02 +02:00
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/// use stm32wlxx_hal::subghz::BitSync;
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2021-08-31 14:32:48 +02:00
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///
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/// const BIT_SYNC: BitSync = BitSync::RESET.set_simple_bit_sync_en(true);
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/// # assert_eq!(u8::from(BIT_SYNC), 0x40u8);
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/// ```
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#[must_use = "set_simple_bit_sync_en returns a modified BitSync"]
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pub const fn set_simple_bit_sync_en(mut self, en: bool) -> BitSync {
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if en {
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self.val |= 1 << 6;
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} else {
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self.val &= !(1 << 6);
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}
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self
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}
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/// Returns `true` if simple bit synchronization is enabled.
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///
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/// # Example
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///
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/// ```
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2022-06-14 16:22:02 +02:00
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/// use stm32wlxx_hal::subghz::BitSync;
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2021-08-31 14:32:48 +02:00
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///
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/// let bs: BitSync = BitSync::RESET;
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/// assert_eq!(bs.simple_bit_sync_en(), false);
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/// let bs: BitSync = bs.set_simple_bit_sync_en(true);
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/// assert_eq!(bs.simple_bit_sync_en(), true);
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/// let bs: BitSync = bs.set_simple_bit_sync_en(false);
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/// assert_eq!(bs.simple_bit_sync_en(), false);
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/// ```
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pub const fn simple_bit_sync_en(&self) -> bool {
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self.val & (1 << 6) != 0
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}
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/// LoRa RX data inversion.
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///
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/// # Example
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///
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/// Invert receive data.
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///
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/// ```
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2022-06-14 16:22:02 +02:00
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/// use stm32wlxx_hal::subghz::BitSync;
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2021-08-31 14:32:48 +02:00
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///
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/// const BIT_SYNC: BitSync = BitSync::RESET.set_rx_data_inv(true);
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/// # assert_eq!(u8::from(BIT_SYNC), 0x20u8);
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/// ```
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#[must_use = "set_rx_data_inv returns a modified BitSync"]
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pub const fn set_rx_data_inv(mut self, inv: bool) -> BitSync {
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if inv {
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self.val |= 1 << 5;
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} else {
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self.val &= !(1 << 5);
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}
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self
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}
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/// Returns `true` if LoRa RX data is inverted.
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///
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/// # Example
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///
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/// ```
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2022-06-14 16:22:02 +02:00
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/// use stm32wlxx_hal::subghz::BitSync;
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2021-08-31 14:32:48 +02:00
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///
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/// let bs: BitSync = BitSync::RESET;
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/// assert_eq!(bs.rx_data_inv(), false);
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/// let bs: BitSync = bs.set_rx_data_inv(true);
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/// assert_eq!(bs.rx_data_inv(), true);
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/// let bs: BitSync = bs.set_rx_data_inv(false);
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/// assert_eq!(bs.rx_data_inv(), false);
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/// ```
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pub const fn rx_data_inv(&self) -> bool {
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self.val & (1 << 5) != 0
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}
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/// LoRa normal bit synchronization enable.
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///
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/// # Example
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///
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/// Enable normal bit synchronization.
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///
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/// ```
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2022-06-14 16:22:02 +02:00
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/// use stm32wlxx_hal::subghz::BitSync;
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2021-08-31 14:32:48 +02:00
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///
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/// const BIT_SYNC: BitSync = BitSync::RESET.set_norm_bit_sync_en(true);
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/// # assert_eq!(u8::from(BIT_SYNC), 0x10u8);
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/// ```
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#[must_use = "set_norm_bit_sync_en returns a modified BitSync"]
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pub const fn set_norm_bit_sync_en(mut self, en: bool) -> BitSync {
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if en {
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self.val |= 1 << 4;
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} else {
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self.val &= !(1 << 4);
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}
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self
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}
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/// Returns `true` if normal bit synchronization is enabled.
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///
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/// # Example
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///
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/// ```
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2022-06-14 16:22:02 +02:00
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/// use stm32wlxx_hal::subghz::BitSync;
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2021-08-31 14:32:48 +02:00
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///
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/// let bs: BitSync = BitSync::RESET;
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/// assert_eq!(bs.norm_bit_sync_en(), false);
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/// let bs: BitSync = bs.set_norm_bit_sync_en(true);
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/// assert_eq!(bs.norm_bit_sync_en(), true);
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/// let bs: BitSync = bs.set_norm_bit_sync_en(false);
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/// assert_eq!(bs.norm_bit_sync_en(), false);
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/// ```
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pub const fn norm_bit_sync_en(&self) -> bool {
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self.val & (1 << 4) != 0
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}
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}
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impl From<BitSync> for u8 {
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fn from(bs: BitSync) -> Self {
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bs.val
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}
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}
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impl Default for BitSync {
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fn default() -> Self {
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Self::RESET
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}
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}
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