2021-01-18 14:22:55 +01:00
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#![no_std]
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#![no_main]
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2021-03-17 02:48:16 +01:00
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#![feature(min_type_alias_impl_trait)]
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#![feature(impl_trait_in_bindings)]
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2021-01-18 14:22:55 +01:00
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#![feature(type_alias_impl_trait)]
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2021-03-27 03:12:58 +01:00
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#![allow(incomplete_features)]
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2021-01-18 14:22:55 +01:00
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#[path = "../example_common.rs"]
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mod example_common;
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use defmt::panic;
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2021-03-29 02:47:10 +02:00
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use embassy::executor::Spawner;
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2021-03-27 03:12:58 +01:00
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use embassy::util::Steal;
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2021-03-21 21:58:59 +01:00
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use embassy_nrf::gpio::{Level, Output, OutputDrive};
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2021-03-29 02:47:10 +02:00
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use embassy_nrf::Peripherals;
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use embassy_nrf::{interrupt, spim};
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2021-03-21 21:58:59 +01:00
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use embassy_traits::spi::FullDuplex;
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2021-01-18 14:22:55 +01:00
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use embedded_hal::digital::v2::*;
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2021-03-21 21:58:59 +01:00
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use example_common::*;
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2021-01-18 14:22:55 +01:00
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2021-03-29 02:47:10 +02:00
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#[embassy::main]
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async fn main(spawner: Spawner) {
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2021-01-18 14:22:55 +01:00
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info!("running!");
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2021-03-27 03:12:58 +01:00
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let p = unsafe { Peripherals::steal() };
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2021-01-18 14:22:55 +01:00
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let config = spim::Config {
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frequency: spim::Frequency::M16,
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mode: spim::MODE_0,
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orc: 0x00,
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};
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2021-03-21 21:58:59 +01:00
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let irq = interrupt::take!(SPIM3);
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2021-04-14 16:37:10 +02:00
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let mut spim = spim::Spim::new(p.SPIM3, irq, p.P0_29, p.P0_28, p.P0_30, config);
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2021-01-18 14:22:55 +01:00
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2021-03-27 03:12:58 +01:00
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let mut ncs = Output::new(p.P0_31, Level::High, OutputDrive::Standard);
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2021-03-19 04:08:44 +01:00
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2021-01-18 14:22:55 +01:00
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// Example on how to talk to an ENC28J60 chip
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// softreset
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cortex_m::asm::delay(10);
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ncs.set_low().unwrap();
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cortex_m::asm::delay(5);
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let tx = [0xFF];
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2021-04-14 16:37:10 +02:00
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unwrap!(spim.read_write(&mut [], &tx).await);
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2021-01-18 14:22:55 +01:00
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cortex_m::asm::delay(10);
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ncs.set_high().unwrap();
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cortex_m::asm::delay(100000);
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let mut rx = [0; 2];
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// read ESTAT
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cortex_m::asm::delay(5000);
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ncs.set_low().unwrap();
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cortex_m::asm::delay(5000);
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let tx = [0b000_11101, 0];
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2021-04-14 16:37:10 +02:00
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unwrap!(spim.read_write(&mut rx, &tx).await);
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2021-01-18 14:22:55 +01:00
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cortex_m::asm::delay(5000);
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ncs.set_high().unwrap();
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info!("estat: {=[?]}", rx);
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// Switch to bank 3
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cortex_m::asm::delay(10);
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ncs.set_low().unwrap();
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cortex_m::asm::delay(5);
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let tx = [0b100_11111, 0b11];
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2021-04-14 16:37:10 +02:00
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unwrap!(spim.read_write(&mut rx, &tx).await);
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2021-01-18 14:22:55 +01:00
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cortex_m::asm::delay(10);
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ncs.set_high().unwrap();
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// read EREVID
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cortex_m::asm::delay(10);
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ncs.set_low().unwrap();
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cortex_m::asm::delay(5);
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let tx = [0b000_10010, 0];
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2021-04-14 16:37:10 +02:00
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unwrap!(spim.read_write(&mut rx, &tx).await);
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2021-01-18 14:22:55 +01:00
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cortex_m::asm::delay(10);
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ncs.set_high().unwrap();
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info!("erevid: {=[?]}", rx);
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}
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