2022-05-02 15:36:02 +02:00
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use core::ptr::write_volatile;
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2023-03-25 16:04:45 +01:00
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use atomic_polyfill::{fence, Ordering};
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2023-03-30 08:32:36 +02:00
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use super::{FlashRegion, FlashSector, FLASH_REGIONS, WRITE_SIZE};
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2022-05-02 15:36:02 +02:00
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use crate::flash::Error;
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use crate::pac;
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2023-05-23 22:50:41 +02:00
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pub const fn set_default_layout() {}
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2023-03-31 15:47:45 +02:00
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pub const fn get_flash_regions() -> &'static [&'static FlashRegion] {
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2023-03-30 08:32:36 +02:00
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&FLASH_REGIONS
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}
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2023-05-24 12:17:12 +02:00
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pub(crate) unsafe fn on_interrupt(_: *mut ()) {
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unimplemented!();
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}
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2022-05-02 15:36:02 +02:00
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pub(crate) unsafe fn lock() {
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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pac::FLASH.cr().modify(|w| w.set_lock(true));
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#[cfg(any(flash_l0))]
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pac::FLASH.pecr().modify(|w| {
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w.set_optlock(true);
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w.set_prglock(true);
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w.set_pelock(true);
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});
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}
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pub(crate) unsafe fn unlock() {
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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{
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pac::FLASH.keyr().write(|w| w.set_keyr(0x4567_0123));
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pac::FLASH.keyr().write(|w| w.set_keyr(0xCDEF_89AB));
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}
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#[cfg(any(flash_l0, flash_l1))]
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{
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pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x89ABCDEF));
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pac::FLASH.pekeyr().write(|w| w.set_pekeyr(0x02030405));
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pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x8C9DAEBF));
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pac::FLASH.prgkeyr().write(|w| w.set_prgkeyr(0x13141516));
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}
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}
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2023-05-24 12:17:12 +02:00
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pub(crate) unsafe fn enable_blocking_write() {
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2023-03-25 16:04:45 +01:00
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assert_eq!(0, WRITE_SIZE % 4);
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2022-05-02 15:36:02 +02:00
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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pac::FLASH.cr().write(|w| w.set_pg(true));
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2023-03-25 16:04:45 +01:00
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}
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2022-05-02 15:36:02 +02:00
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2023-05-24 12:17:12 +02:00
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pub(crate) unsafe fn disable_blocking_write() {
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2022-05-02 15:36:02 +02:00
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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pac::FLASH.cr().write(|w| w.set_pg(false));
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2023-03-25 16:04:45 +01:00
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}
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2023-05-24 12:17:12 +02:00
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pub(crate) unsafe fn write_blocking(start_address: u32, buf: &[u8; WRITE_SIZE]) -> Result<(), Error> {
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2023-03-25 16:04:45 +01:00
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let mut address = start_address;
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for val in buf.chunks(4) {
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write_volatile(address as *mut u32, u32::from_le_bytes(val.try_into().unwrap()));
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address += val.len() as u32;
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// prevents parallelism errors
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fence(Ordering::SeqCst);
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}
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2023-05-24 12:17:12 +02:00
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wait_ready_blocking()
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2023-03-25 16:04:45 +01:00
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}
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2022-05-02 15:36:02 +02:00
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2023-05-24 12:17:12 +02:00
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pub(crate) unsafe fn erase_sector_blocking(sector: &FlashSector) -> Result<(), Error> {
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2023-03-29 13:37:10 +02:00
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#[cfg(any(flash_l0, flash_l1))]
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{
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2022-05-02 15:36:02 +02:00
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pac::FLASH.pecr().modify(|w| {
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2023-03-29 13:37:10 +02:00
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w.set_erase(true);
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w.set_prog(true);
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2022-05-02 15:36:02 +02:00
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});
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2023-03-29 13:37:10 +02:00
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write_volatile(sector.start as *mut u32, 0xFFFFFFFF);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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{
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2023-03-30 08:32:36 +02:00
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let idx = (sector.start - super::FLASH_BASE as u32) / super::BANK1_REGION.erase_size as u32;
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2023-03-29 13:37:10 +02:00
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#[cfg(flash_l4)]
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let (idx, bank) = if idx > 255 { (idx - 256, true) } else { (idx, false) };
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pac::FLASH.cr().modify(|w| {
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w.set_per(true);
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w.set_pnb(idx as u8);
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#[cfg(any(flash_wl, flash_wb))]
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w.set_strt(true);
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#[cfg(any(flash_l4))]
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w.set_start(true);
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#[cfg(any(flash_l4))]
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w.set_bker(bank);
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});
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2022-05-02 15:36:02 +02:00
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}
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2023-05-24 12:17:12 +02:00
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let ret: Result<(), Error> = wait_ready_blocking();
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2023-03-29 13:37:10 +02:00
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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pac::FLASH.cr().modify(|w| w.set_per(false));
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#[cfg(any(flash_l0, flash_l1))]
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pac::FLASH.pecr().modify(|w| {
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w.set_erase(false);
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w.set_prog(false);
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});
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clear_all_err();
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ret
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2022-05-02 15:36:02 +02:00
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}
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pub(crate) unsafe fn clear_all_err() {
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pac::FLASH.sr().modify(|w| {
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#[cfg(any(flash_wl, flash_wb, flash_l4, flash_l0))]
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if w.rderr() {
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w.set_rderr(true);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.fasterr() {
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w.set_fasterr(true);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.miserr() {
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w.set_miserr(true);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.pgserr() {
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w.set_pgserr(true);
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}
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if w.sizerr() {
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w.set_sizerr(true);
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}
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if w.pgaerr() {
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w.set_pgaerr(true);
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}
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if w.wrperr() {
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w.set_wrperr(true);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.progerr() {
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w.set_progerr(true);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if w.operr() {
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w.set_operr(true);
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}
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});
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}
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2023-05-24 12:17:12 +02:00
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unsafe fn wait_ready_blocking() -> Result<(), Error> {
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2022-05-02 15:36:02 +02:00
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loop {
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let sr = pac::FLASH.sr().read();
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if !sr.bsy() {
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if sr.progerr() {
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return Err(Error::Prog);
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}
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if sr.wrperr() {
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return Err(Error::Protected);
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}
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if sr.pgaerr() {
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return Err(Error::Unaligned);
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}
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if sr.sizerr() {
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return Err(Error::Size);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if sr.miserr() {
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return Err(Error::Miss);
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}
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#[cfg(any(flash_wl, flash_wb, flash_l4))]
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if sr.pgserr() {
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return Err(Error::Seq);
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}
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return Ok(());
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}
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}
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}
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