106 lines
4.9 KiB
Rust
106 lines
4.9 KiB
Rust
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#![allow(unused)]
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pub(crate) const FUNC_BUS: u32 = 0;
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pub(crate) const FUNC_BACKPLANE: u32 = 1;
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pub(crate) const FUNC_WLAN: u32 = 2;
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pub(crate) const FUNC_BT: u32 = 3;
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pub(crate) const REG_BUS_CTRL: u32 = 0x0;
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pub(crate) const REG_BUS_INTERRUPT: u32 = 0x04; // 16 bits - Interrupt status
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pub(crate) const REG_BUS_INTERRUPT_ENABLE: u32 = 0x06; // 16 bits - Interrupt mask
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pub(crate) const REG_BUS_STATUS: u32 = 0x8;
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pub(crate) const REG_BUS_TEST_RO: u32 = 0x14;
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pub(crate) const REG_BUS_TEST_RW: u32 = 0x18;
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pub(crate) const REG_BUS_RESP_DELAY: u32 = 0x1c;
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pub(crate) const WORD_LENGTH_32: u32 = 0x1;
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pub(crate) const HIGH_SPEED: u32 = 0x10;
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// SPI_STATUS_REGISTER bits
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pub(crate) const STATUS_DATA_NOT_AVAILABLE: u32 = 0x00000001;
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pub(crate) const STATUS_UNDERFLOW: u32 = 0x00000002;
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pub(crate) const STATUS_OVERFLOW: u32 = 0x00000004;
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pub(crate) const STATUS_F2_INTR: u32 = 0x00000008;
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pub(crate) const STATUS_F3_INTR: u32 = 0x00000010;
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pub(crate) const STATUS_F2_RX_READY: u32 = 0x00000020;
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pub(crate) const STATUS_F3_RX_READY: u32 = 0x00000040;
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pub(crate) const STATUS_HOST_CMD_DATA_ERR: u32 = 0x00000080;
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pub(crate) const STATUS_F2_PKT_AVAILABLE: u32 = 0x00000100;
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pub(crate) const STATUS_F2_PKT_LEN_MASK: u32 = 0x000FFE00;
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pub(crate) const STATUS_F2_PKT_LEN_SHIFT: u32 = 9;
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pub(crate) const STATUS_F3_PKT_AVAILABLE: u32 = 0x00100000;
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pub(crate) const STATUS_F3_PKT_LEN_MASK: u32 = 0xFFE00000;
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pub(crate) const STATUS_F3_PKT_LEN_SHIFT: u32 = 21;
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pub(crate) const REG_BACKPLANE_GPIO_SELECT: u32 = 0x10005;
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pub(crate) const REG_BACKPLANE_GPIO_OUTPUT: u32 = 0x10006;
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pub(crate) const REG_BACKPLANE_GPIO_ENABLE: u32 = 0x10007;
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pub(crate) const REG_BACKPLANE_FUNCTION2_WATERMARK: u32 = 0x10008;
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pub(crate) const REG_BACKPLANE_DEVICE_CONTROL: u32 = 0x10009;
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pub(crate) const REG_BACKPLANE_BACKPLANE_ADDRESS_LOW: u32 = 0x1000A;
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pub(crate) const REG_BACKPLANE_BACKPLANE_ADDRESS_MID: u32 = 0x1000B;
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pub(crate) const REG_BACKPLANE_BACKPLANE_ADDRESS_HIGH: u32 = 0x1000C;
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pub(crate) const REG_BACKPLANE_FRAME_CONTROL: u32 = 0x1000D;
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pub(crate) const REG_BACKPLANE_CHIP_CLOCK_CSR: u32 = 0x1000E;
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pub(crate) const REG_BACKPLANE_PULL_UP: u32 = 0x1000F;
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pub(crate) const REG_BACKPLANE_READ_FRAME_BC_LOW: u32 = 0x1001B;
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pub(crate) const REG_BACKPLANE_READ_FRAME_BC_HIGH: u32 = 0x1001C;
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pub(crate) const REG_BACKPLANE_WAKEUP_CTRL: u32 = 0x1001E;
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pub(crate) const REG_BACKPLANE_SLEEP_CSR: u32 = 0x1001F;
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pub(crate) const BACKPLANE_WINDOW_SIZE: usize = 0x8000;
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pub(crate) const BACKPLANE_ADDRESS_MASK: u32 = 0x7FFF;
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pub(crate) const BACKPLANE_ADDRESS_32BIT_FLAG: u32 = 0x08000;
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pub(crate) const BACKPLANE_MAX_TRANSFER_SIZE: usize = 64;
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// Active Low Power (ALP) clock constants
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pub(crate) const BACKPLANE_ALP_AVAIL_REQ: u8 = 0x08;
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pub(crate) const BACKPLANE_ALP_AVAIL: u8 = 0x40;
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// Broadcom AMBA (Advanced Microcontroller Bus Architecture) Interconnect
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// (AI) pub (crate) constants
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pub(crate) const AI_IOCTRL_OFFSET: u32 = 0x408;
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pub(crate) const AI_IOCTRL_BIT_FGC: u8 = 0x0002;
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pub(crate) const AI_IOCTRL_BIT_CLOCK_EN: u8 = 0x0001;
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pub(crate) const AI_IOCTRL_BIT_CPUHALT: u8 = 0x0020;
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pub(crate) const AI_RESETCTRL_OFFSET: u32 = 0x800;
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pub(crate) const AI_RESETCTRL_BIT_RESET: u8 = 1;
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pub(crate) const AI_RESETSTATUS_OFFSET: u32 = 0x804;
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pub(crate) const TEST_PATTERN: u32 = 0x12345678;
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pub(crate) const FEEDBEAD: u32 = 0xFEEDBEAD;
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// SPI_INTERRUPT_REGISTER and SPI_INTERRUPT_ENABLE_REGISTER Bits
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pub(crate) const IRQ_DATA_UNAVAILABLE: u16 = 0x0001; // Requested data not available; Clear by writing a "1"
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pub(crate) const IRQ_F2_F3_FIFO_RD_UNDERFLOW: u16 = 0x0002;
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pub(crate) const IRQ_F2_F3_FIFO_WR_OVERFLOW: u16 = 0x0004;
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pub(crate) const IRQ_COMMAND_ERROR: u16 = 0x0008; // Cleared by writing 1
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pub(crate) const IRQ_DATA_ERROR: u16 = 0x0010; // Cleared by writing 1
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pub(crate) const IRQ_F2_PACKET_AVAILABLE: u16 = 0x0020;
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pub(crate) const IRQ_F3_PACKET_AVAILABLE: u16 = 0x0040;
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pub(crate) const IRQ_F1_OVERFLOW: u16 = 0x0080; // Due to last write. Bkplane has pending write requests
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pub(crate) const IRQ_MISC_INTR0: u16 = 0x0100;
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pub(crate) const IRQ_MISC_INTR1: u16 = 0x0200;
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pub(crate) const IRQ_MISC_INTR2: u16 = 0x0400;
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pub(crate) const IRQ_MISC_INTR3: u16 = 0x0800;
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pub(crate) const IRQ_MISC_INTR4: u16 = 0x1000;
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pub(crate) const IRQ_F1_INTR: u16 = 0x2000;
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pub(crate) const IRQ_F2_INTR: u16 = 0x4000;
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pub(crate) const IRQ_F3_INTR: u16 = 0x8000;
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pub(crate) const IOCTL_CMD_UP: u32 = 2;
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pub(crate) const IOCTL_CMD_SET_SSID: u32 = 26;
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pub(crate) const IOCTL_CMD_ANTDIV: u32 = 64;
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pub(crate) const IOCTL_CMD_SET_VAR: u32 = 263;
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pub(crate) const IOCTL_CMD_GET_VAR: u32 = 262;
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pub(crate) const IOCTL_CMD_SET_PASSPHRASE: u32 = 268;
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pub(crate) const CHANNEL_TYPE_CONTROL: u8 = 0;
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pub(crate) const CHANNEL_TYPE_EVENT: u8 = 1;
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pub(crate) const CHANNEL_TYPE_DATA: u8 = 2;
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// CYW_SPID command structure constants.
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pub(crate) const WRITE: bool = true;
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pub(crate) const READ: bool = false;
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pub(crate) const INC_ADDR: bool = true;
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pub(crate) const FIXED_ADDR: bool = false;
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