2022-03-19 11:05:00 +01:00
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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2022-06-12 22:15:44 +02:00
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use defmt::*;
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2022-08-17 23:40:16 +02:00
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use embassy_executor::Spawner;
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2022-03-19 11:05:00 +01:00
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use embassy_stm32::adc::{Adc, SampleTime};
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2022-08-17 18:49:55 +02:00
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use embassy_stm32::Config;
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2022-08-17 23:40:16 +02:00
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use embassy_time::{Delay, Duration, Timer};
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2022-06-12 22:15:44 +02:00
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use {defmt_rtt as _, panic_probe as _};
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2022-03-19 11:05:00 +01:00
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2022-08-17 22:25:58 +02:00
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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2022-03-19 11:05:00 +01:00
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let mut config = Config::default();
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2023-09-19 04:22:57 +02:00
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{
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use embassy_stm32::rcc::*;
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config.rcc.hsi = Some(Hsi::Mhz64);
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config.rcc.csi = true;
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config.rcc.pll_src = PllSource::Hsi;
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config.rcc.pll1 = Some(Pll {
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prediv: 4,
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mul: 50,
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divp: Some(2),
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divq: Some(8), // SPI1 cksel defaults to pll1_q
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divr: None,
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});
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config.rcc.pll2 = Some(Pll {
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prediv: 4,
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mul: 50,
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divp: Some(8), // 100mhz
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divq: None,
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divr: None,
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});
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config.rcc.sys = Sysclk::Pll1P; // 400 Mhz
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config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
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config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
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config.rcc.voltage_scale = VoltageScale::Scale1;
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config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
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}
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2022-08-17 22:25:58 +02:00
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let mut p = embassy_stm32::init(config);
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2022-03-19 11:05:00 +01:00
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info!("Hello World!");
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let mut adc = Adc::new(p.ADC3, &mut Delay);
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adc.set_sample_time(SampleTime::Cycles32_5);
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2022-07-27 00:17:26 +02:00
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let mut vrefint_channel = adc.enable_vrefint();
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2022-03-19 11:05:00 +01:00
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loop {
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2022-07-27 00:17:26 +02:00
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let vrefint = adc.read_internal(&mut vrefint_channel);
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info!("vrefint: {}", vrefint);
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2022-03-19 11:05:00 +01:00
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let measured = adc.read(&mut p.PC0);
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info!("measured: {}", measured);
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Timer::after(Duration::from_millis(500)).await;
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}
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}
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