2022-03-16 22:44:02 +01:00
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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2022-04-02 04:35:06 +02:00
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use defmt::*;
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2022-08-17 23:40:16 +02:00
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use embassy_executor::Spawner;
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2022-03-16 22:44:02 +01:00
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use embassy_stm32::sdmmc::Sdmmc;
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2023-10-18 03:16:36 +02:00
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use embassy_stm32::time::{mhz, Hertz};
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2023-05-25 00:29:56 +02:00
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use embassy_stm32::{bind_interrupts, peripherals, sdmmc, Config};
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2022-06-12 22:15:44 +02:00
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use {defmt_rtt as _, panic_probe as _};
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2022-03-16 22:44:02 +01:00
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2023-05-25 00:29:56 +02:00
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bind_interrupts!(struct Irqs {
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SDMMC1 => sdmmc::InterruptHandler<peripherals::SDMMC1>;
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});
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2022-08-17 22:25:58 +02:00
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#[embassy_executor::main]
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2023-03-08 03:08:59 +01:00
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async fn main(_spawner: Spawner) {
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2022-03-16 22:44:02 +01:00
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let mut config = Config::default();
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2023-10-18 03:16:36 +02:00
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{
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use embassy_stm32::rcc::*;
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config.rcc.hse = Some(Hse {
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freq: Hertz(8_000_000),
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mode: HseMode::Bypass,
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});
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config.rcc.pll_src = PllSource::HSE;
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config.rcc.pll = Some(Pll {
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prediv: PllPreDiv::DIV4,
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mul: PllMul::MUL216,
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divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
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divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
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divr: None,
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});
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config.rcc.ahb_pre = AHBPrescaler::DIV1;
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config.rcc.apb1_pre = APBPrescaler::DIV4;
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config.rcc.apb2_pre = APBPrescaler::DIV2;
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config.rcc.sys = Sysclk::PLL1_P;
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}
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2022-08-17 22:25:58 +02:00
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let p = embassy_stm32::init(config);
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2022-03-16 22:44:02 +01:00
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info!("Hello World!");
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2022-07-23 01:29:35 +02:00
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let mut sdmmc = Sdmmc::new_4bit(
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2022-03-16 22:44:02 +01:00
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p.SDMMC1,
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2023-05-25 00:29:56 +02:00
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Irqs,
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2022-03-16 23:03:24 +01:00
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p.DMA2_CH3,
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2022-07-23 01:29:35 +02:00
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p.PC12,
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p.PD2,
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p.PC8,
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p.PC9,
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p.PC10,
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p.PC11,
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Default::default(),
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2022-03-16 22:44:02 +01:00
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);
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2022-03-16 22:55:07 +01:00
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// Should print 400kHz for initialization
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info!("Configured clock: {}", sdmmc.clock().0);
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2022-03-16 22:44:02 +01:00
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2022-07-11 00:36:10 +02:00
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unwrap!(sdmmc.init_card(mhz(25)).await);
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2022-03-16 22:44:02 +01:00
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let card = unwrap!(sdmmc.card());
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info!("Card: {:#?}", Debug2Format(card));
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}
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