2021-06-10 21:33:43 +02:00
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use core::marker::PhantomData;
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2022-06-12 22:15:44 +02:00
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2022-07-23 14:00:19 +02:00
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use embassy_hal_common::into_ref;
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2022-01-26 22:39:06 +01:00
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use embedded_hal_02::blocking::delay::DelayUs;
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2021-06-10 21:33:43 +02:00
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2022-10-26 09:04:52 +02:00
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use crate::adc::{AdcPin, Instance, Resolution, SampleTime};
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2022-07-23 14:00:19 +02:00
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use crate::Peripheral;
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2022-06-12 22:15:44 +02:00
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2022-07-27 00:17:26 +02:00
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/// Default VREF voltage used for sample conversion to millivolts.
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pub const VREF_DEFAULT_MV: u32 = 3300;
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/// VREF voltage used for factory calibration of VREFINTCAL register.
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pub const VREF_CALIB_MV: u32 = 3000;
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2021-06-10 21:33:43 +02:00
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2021-09-29 02:29:46 +02:00
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/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock
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/// configuration.
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2022-03-18 00:11:57 +01:00
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fn enable() {
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critical_section::with(|_| unsafe {
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#[cfg(stm32h7)]
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crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
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#[cfg(stm32g0)]
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crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
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2022-04-08 02:57:48 +02:00
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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2022-03-18 00:11:57 +01:00
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crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
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});
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2021-09-29 02:29:46 +02:00
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}
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2022-07-27 00:17:26 +02:00
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pub struct VrefInt;
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impl<T: Instance> AdcPin<T> for VrefInt {}
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impl<T: Instance> super::sealed::AdcPin<T> for VrefInt {
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2021-06-10 21:33:43 +02:00
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fn channel(&self) -> u8 {
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2022-02-24 05:59:42 +01:00
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#[cfg(not(stm32g0))]
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2021-08-30 21:34:37 +02:00
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let val = 0;
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2022-02-24 05:59:42 +01:00
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#[cfg(stm32g0)]
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2021-08-30 21:34:37 +02:00
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let val = 13;
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val
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2021-06-10 21:33:43 +02:00
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}
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}
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pub struct Temperature;
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impl<T: Instance> AdcPin<T> for Temperature {}
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impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
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fn channel(&self) -> u8 {
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2022-02-24 05:59:42 +01:00
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#[cfg(not(stm32g0))]
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2021-08-30 21:34:37 +02:00
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let val = 17;
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2022-02-24 05:59:42 +01:00
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#[cfg(stm32g0)]
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2021-08-30 21:34:37 +02:00
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let val = 12;
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val
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2021-06-10 21:33:43 +02:00
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}
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}
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pub struct Vbat;
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impl<T: Instance> AdcPin<T> for Vbat {}
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impl<T: Instance> super::sealed::AdcPin<T> for Vbat {
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fn channel(&self) -> u8 {
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2022-02-24 05:59:42 +01:00
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#[cfg(not(stm32g0))]
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2021-08-30 21:34:37 +02:00
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let val = 18;
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2022-02-24 05:59:42 +01:00
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#[cfg(stm32g0)]
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2021-08-30 21:34:37 +02:00
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let val = 14;
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val
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2021-06-10 21:33:43 +02:00
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}
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}
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pub struct Adc<'d, T: Instance> {
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sample_time: SampleTime,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Adc<'d, T> {
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2022-07-23 14:00:19 +02:00
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pub fn new(_peri: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
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into_ref!(_peri);
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2022-03-18 00:11:57 +01:00
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enable();
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2021-06-10 21:33:43 +02:00
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unsafe {
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T::regs().cr().modify(|reg| {
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2021-08-30 21:34:37 +02:00
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#[cfg(not(adc_g0))]
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2021-06-10 21:33:43 +02:00
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reg.set_deeppwd(false);
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reg.set_advregen(true);
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});
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2021-08-30 21:34:37 +02:00
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#[cfg(adc_g0)]
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T::regs().cfgr1().modify(|reg| {
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reg.set_chselrmod(true);
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});
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2021-06-10 21:33:43 +02:00
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}
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delay.delay_us(20);
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unsafe {
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2021-08-30 21:34:37 +02:00
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T::regs().cr().modify(|reg| {
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reg.set_adcal(true);
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});
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2021-06-10 21:33:43 +02:00
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while T::regs().cr().read().adcal() {
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// spin
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}
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}
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delay.delay_us(1);
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2021-07-05 03:09:42 +02:00
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Self {
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sample_time: Default::default(),
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phantom: PhantomData,
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}
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2021-06-10 21:33:43 +02:00
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}
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2022-07-27 00:17:26 +02:00
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pub fn enable_vrefint(&self, delay: &mut impl DelayUs<u32>) -> VrefInt {
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2021-06-10 21:33:43 +02:00
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unsafe {
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T::common_regs().ccr().modify(|reg| {
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reg.set_vrefen(true);
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});
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}
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// "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
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// to stabilize the internal voltage reference, we wait a little more.
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// TODO: delay 15us
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//cortex_m::asm::delay(20_000_000);
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delay.delay_us(15);
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2022-07-27 00:17:26 +02:00
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VrefInt {}
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2021-06-10 21:33:43 +02:00
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}
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pub fn enable_temperature(&self) -> Temperature {
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unsafe {
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T::common_regs().ccr().modify(|reg| {
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reg.set_ch17sel(true);
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});
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}
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Temperature {}
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}
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pub fn enable_vbat(&self) -> Vbat {
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unsafe {
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T::common_regs().ccr().modify(|reg| {
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reg.set_ch18sel(true);
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});
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}
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Vbat {}
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}
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pub fn set_sample_time(&mut self, sample_time: SampleTime) {
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self.sample_time = sample_time;
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}
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pub fn set_resolution(&mut self, resolution: Resolution) {
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2022-10-26 23:45:12 +02:00
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unsafe {
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#[cfg(not(stm32g0))]
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T::regs().cfgr().modify(|reg| reg.set_res(resolution.into()));
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#[cfg(stm32g0)]
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T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into()));
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}
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2021-06-10 21:33:43 +02:00
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}
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/*
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/// Convert a raw sample from the `Temperature` to deg C
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pub fn to_degrees_centigrade(sample: u16) -> f32 {
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(130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
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* (sample as f32 - VtempCal30::get().read() as f32)
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+ 30.0
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}
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*/
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2021-08-30 21:33:42 +02:00
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/// Perform a single conversion.
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fn convert(&mut self) -> u16 {
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unsafe {
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T::regs().isr().modify(|reg| {
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reg.set_eos(true);
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reg.set_eoc(true);
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});
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// Start conversion
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T::regs().cr().modify(|reg| {
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reg.set_adstart(true);
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});
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while !T::regs().isr().read().eos() {
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// spin
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}
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T::regs().dr().read().0 as u16
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}
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}
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2021-06-10 21:33:43 +02:00
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pub fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 {
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unsafe {
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// Make sure bits are off
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while T::regs().cr().read().addis() {
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// spin
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}
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// Enable ADC
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T::regs().isr().modify(|reg| {
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reg.set_adrdy(true);
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});
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T::regs().cr().modify(|reg| {
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reg.set_aden(true);
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});
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while !T::regs().isr().read().adrdy() {
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// spin
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}
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// Configure channel
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Self::set_channel_sample_time(pin.channel(), self.sample_time);
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// Select channel
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2022-02-24 05:59:42 +01:00
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#[cfg(not(stm32g0))]
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2021-06-10 21:33:43 +02:00
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T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel()));
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2022-02-24 05:59:42 +01:00
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#[cfg(stm32g0)]
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2022-06-12 22:15:44 +02:00
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T::regs().chselr().write(|reg| reg.set_chsel(pin.channel() as u32));
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2021-06-10 21:33:43 +02:00
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2021-08-30 21:33:42 +02:00
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// Some models are affected by an erratum:
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// If we perform conversions slower than 1 kHz, the first read ADC value can be
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// corrupted, so we discard it and measure again.
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//
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// STM32L471xx: Section 2.7.3
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// STM32G4: Section 2.7.3
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#[cfg(any(rcc_l4, rcc_g4))]
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let _ = self.convert();
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2021-06-10 21:33:43 +02:00
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2021-08-30 21:33:42 +02:00
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let val = self.convert();
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2021-06-10 21:33:43 +02:00
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T::regs().cr().modify(|reg| reg.set_addis(true));
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val
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}
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}
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2022-02-24 05:59:42 +01:00
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#[cfg(stm32g0)]
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2021-08-30 21:34:37 +02:00
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unsafe fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
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2022-10-26 09:28:39 +02:00
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T::regs().smpr().modify(|reg| reg.set_smp1(sample_time.into()));
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2021-08-30 21:34:37 +02:00
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}
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2022-02-24 05:59:42 +01:00
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#[cfg(not(stm32g0))]
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2021-06-10 21:33:43 +02:00
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unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
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2022-10-26 09:28:39 +02:00
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let sample_time = sample_time.into();
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2021-07-03 14:05:12 +02:00
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if ch <= 9 {
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2022-10-26 09:28:39 +02:00
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T::regs().smpr1().modify(|reg| reg.set_smp(ch as _, sample_time));
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2021-06-10 21:33:43 +02:00
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} else {
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2022-10-26 09:28:39 +02:00
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T::regs().smpr2().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
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2021-06-10 21:33:43 +02:00
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}
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}
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}
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