2022-05-26 18:54:58 +02:00
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//! Asynchronous shared SPI bus
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//!
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//! # Example (nrf52)
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//!
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//! ```rust
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2022-07-18 20:01:39 +02:00
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//! use embassy_embedded_hal::shared_bus::spi::SpiDevice;
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2022-08-22 21:46:09 +02:00
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//! use embassy_sync::mutex::Mutex;
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//! use embassy_sync::blocking_mutex::raw::ThreadModeRawMutex;
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2022-05-26 18:54:58 +02:00
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//!
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2022-08-22 15:51:44 +02:00
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//! static SPI_BUS: StaticCell<Mutex<ThreadModeRawMutex, spim::Spim<SPI3>>> = StaticCell::new();
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2022-05-26 18:54:58 +02:00
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//! let mut config = spim::Config::default();
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//! config.frequency = spim::Frequency::M32;
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//! let irq = interrupt::take!(SPIM3);
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//! let spi = spim::Spim::new_txonly(p.SPI3, irq, p.P0_15, p.P0_18, config);
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//! let spi_bus = Mutex::<ThreadModeRawMutex, _>::new(spi);
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2022-08-22 15:51:44 +02:00
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//! let spi_bus = SPI_BUS.init(spi_bus);
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2022-05-26 18:54:58 +02:00
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//!
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//! // Device 1, using embedded-hal-async compatible driver for ST7735 LCD display
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//! let cs_pin1 = Output::new(p.P0_24, Level::Low, OutputDrive::Standard);
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2022-07-18 20:01:39 +02:00
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//! let spi_dev1 = SpiDevice::new(spi_bus, cs_pin1);
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//! let display1 = ST7735::new(spi_dev1, dc1, rst1, Default::default(), 160, 128);
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//!
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//! // Device 2
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//! let cs_pin2 = Output::new(p.P0_24, Level::Low, OutputDrive::Standard);
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2022-07-18 20:01:39 +02:00
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//! let spi_dev2 = SpiDevice::new(spi_bus, cs_pin2);
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2022-05-26 18:54:58 +02:00
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//! let display2 = ST7735::new(spi_dev2, dc2, rst2, Default::default(), 160, 128);
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//! ```
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2022-06-12 22:15:44 +02:00
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use core::future::Future;
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2022-08-22 21:46:09 +02:00
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use embassy_sync::blocking_mutex::raw::RawMutex;
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use embassy_sync::mutex::Mutex;
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2022-09-29 11:02:43 +02:00
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use embedded_hal_1::digital::OutputPin;
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2022-05-26 18:54:58 +02:00
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use embedded_hal_1::spi::ErrorType;
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use embedded_hal_async::spi;
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2022-07-18 20:01:39 +02:00
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use crate::shared_bus::SpiDeviceError;
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2022-07-08 15:47:47 +02:00
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use crate::SetConfig;
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2022-07-19 07:57:39 +02:00
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/// SPI device on a shared bus.
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2022-07-18 20:01:39 +02:00
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pub struct SpiDevice<'a, M: RawMutex, BUS, CS> {
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bus: &'a Mutex<M, BUS>,
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cs: CS,
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}
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2022-07-18 20:01:39 +02:00
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impl<'a, M: RawMutex, BUS, CS> SpiDevice<'a, M, BUS, CS> {
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/// Create a new `SpiDevice`.
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2022-05-26 18:54:58 +02:00
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pub fn new(bus: &'a Mutex<M, BUS>, cs: CS) -> Self {
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Self { bus, cs }
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}
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}
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2022-07-18 20:01:39 +02:00
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impl<'a, M: RawMutex, BUS, CS> spi::ErrorType for SpiDevice<'a, M, BUS, CS>
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where
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BUS: spi::ErrorType,
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CS: OutputPin,
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{
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type Error = SpiDeviceError<BUS::Error, CS::Error>;
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}
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2022-09-29 11:02:43 +02:00
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unsafe impl<M, BUS, CS> spi::SpiDevice for SpiDevice<'_, M, BUS, CS>
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where
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M: RawMutex + 'static,
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BUS: spi::SpiBusFlush + 'static,
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CS: OutputPin,
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{
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type Bus = BUS;
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2022-11-21 23:31:31 +01:00
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async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
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2022-05-26 18:54:58 +02:00
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where
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F: FnOnce(*mut Self::Bus) -> Fut,
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Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
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{
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let mut bus = self.bus.lock().await;
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self.cs.set_low().map_err(SpiDeviceError::Cs)?;
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2022-11-21 23:31:31 +01:00
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let f_res = f(&mut *bus).await;
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2022-05-26 18:54:58 +02:00
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2022-11-21 23:31:31 +01:00
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// On failure, it's important to still flush and deassert CS.
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let flush_res = bus.flush().await;
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let cs_res = self.cs.set_high();
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2022-05-26 18:54:58 +02:00
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2022-11-21 23:31:31 +01:00
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let f_res = f_res.map_err(SpiDeviceError::Spi)?;
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flush_res.map_err(SpiDeviceError::Spi)?;
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cs_res.map_err(SpiDeviceError::Cs)?;
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2022-11-21 23:31:31 +01:00
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Ok(f_res)
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2022-05-26 18:54:58 +02:00
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}
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}
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2022-07-08 15:47:47 +02:00
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2022-07-19 07:57:39 +02:00
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/// SPI device on a shared bus, with its own configuration.
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///
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/// This is like [`SpiDevice`], with an additional bus configuration that's applied
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/// to the bus before each use using [`SetConfig`]. This allows different
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/// devices on the same bus to use different communication settings.
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2022-07-18 20:01:39 +02:00
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pub struct SpiDeviceWithConfig<'a, M: RawMutex, BUS: SetConfig, CS> {
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bus: &'a Mutex<M, BUS>,
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cs: CS,
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config: BUS::Config,
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}
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2022-07-18 20:01:39 +02:00
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impl<'a, M: RawMutex, BUS: SetConfig, CS> SpiDeviceWithConfig<'a, M, BUS, CS> {
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/// Create a new `SpiDeviceWithConfig`.
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2022-07-09 00:00:55 +02:00
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pub fn new(bus: &'a Mutex<M, BUS>, cs: CS, config: BUS::Config) -> Self {
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Self { bus, cs, config }
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}
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}
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2022-07-18 20:01:39 +02:00
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impl<'a, M, BUS, CS> spi::ErrorType for SpiDeviceWithConfig<'a, M, BUS, CS>
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where
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BUS: spi::ErrorType + SetConfig,
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CS: OutputPin,
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M: RawMutex,
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{
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type Error = SpiDeviceError<BUS::Error, CS::Error>;
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}
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2022-09-29 11:02:43 +02:00
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unsafe impl<M, BUS, CS> spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS>
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where
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M: RawMutex + 'static,
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BUS: spi::SpiBusFlush + SetConfig + 'static,
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CS: OutputPin,
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{
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type Bus = BUS;
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2022-11-21 23:31:31 +01:00
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async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
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2022-07-08 15:47:47 +02:00
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where
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2022-11-21 23:31:31 +01:00
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F: FnOnce(*mut Self::Bus) -> Fut,
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Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
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{
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2022-11-21 23:31:31 +01:00
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let mut bus = self.bus.lock().await;
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bus.set_config(&self.config);
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self.cs.set_low().map_err(SpiDeviceError::Cs)?;
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2022-07-08 15:47:47 +02:00
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2022-11-21 23:31:31 +01:00
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let f_res = f(&mut *bus).await;
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2022-07-08 15:47:47 +02:00
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2022-11-21 23:31:31 +01:00
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// On failure, it's important to still flush and deassert CS.
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let flush_res = bus.flush().await;
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let cs_res = self.cs.set_high();
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2022-07-08 15:47:47 +02:00
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2022-11-21 23:31:31 +01:00
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let f_res = f_res.map_err(SpiDeviceError::Spi)?;
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flush_res.map_err(SpiDeviceError::Spi)?;
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cs_res.map_err(SpiDeviceError::Cs)?;
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2022-07-08 15:47:47 +02:00
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2022-11-21 23:31:31 +01:00
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Ok(f_res)
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2022-07-08 15:47:47 +02:00
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}
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}
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