72 lines
2.4 KiB
Rust
72 lines
2.4 KiB
Rust
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use crate::pac::peripherals;
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use crate::pac::{PWR, RCC, SYSCFG};
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/// Voltage Scale
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///
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/// Represents the voltage range feeding the CPU core. The maximum core
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/// clock frequency depends on this value.
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#[derive(Copy, Clone, PartialEq)]
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pub enum VoltageScale {
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/// VOS 0 range VCORE 1.26V - 1.40V
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Scale0,
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/// VOS 1 range VCORE 1.15V - 1.26V
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Scale1,
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/// VOS 2 range VCORE 1.05V - 1.15V
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Scale2,
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/// VOS 3 range VCORE 0.95V - 1.05V
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Scale3,
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}
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/// Power Configuration
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///
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/// Generated when the PWR peripheral is frozen. The existence of this
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/// value indicates that the voltage scaling configuration can no
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/// longer be changed.
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pub struct Power {
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pub(crate) vos: VoltageScale,
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}
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impl Power {
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pub fn new(_peri: peripherals::PWR, enable_overdrive: bool) -> Self {
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use crate::pac::rcc::vals::Apb4enrSyscfgen;
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// NOTE(unsafe) we have the PWR singleton
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unsafe {
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// NB. The lower bytes of CR3 can only be written once after
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// POR, and must be written with a valid combination. Refer to
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// RM0433 Rev 7 6.8.4. This is partially enforced by dropping
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// `self` at the end of this method, but of course we cannot
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// know what happened between the previous POR and here.
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PWR.cr3().modify(|w| {
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w.set_scuen(true);
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w.set_ldoen(true);
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w.set_bypass(false);
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});
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// Validate the supply configuration. If you are stuck here, it is
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// because the voltages on your board do not match those specified
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// in the D3CR.VOS and CR3.SDLEVEL fields. By default after reset
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// VOS = Scale 3, so check that the voltage on the VCAP pins =
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// 1.0V.
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while !PWR.csr1().read().actvosrdy() {}
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// Go to Scale 1
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PWR.d3cr().modify(|w| w.set_vos(0b11));
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while !PWR.d3cr().read().vosrdy() {}
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let vos = if !enable_overdrive {
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VoltageScale::Scale1
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} else {
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critical_section::with(|_| {
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RCC.apb4enr()
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.modify(|w| w.set_syscfgen(Apb4enrSyscfgen::ENABLED));
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SYSCFG.pwrcr().modify(|w| w.set_oden(1));
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});
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while !PWR.d3cr().read().vosrdy() {}
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VoltageScale::Scale0
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};
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Self { vos }
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}
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}
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}
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