2021-07-30 22:48:13 +02:00
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use crate::pac;
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use crate::peripherals::{self, RCC};
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use crate::rcc::{get_freqs, set_freqs, Clocks};
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use crate::time::Hertz;
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use crate::time::U32Ext;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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/// HSI speed
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pub const HSI_FREQ: u32 = 16_000_000;
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/// LSI speed
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pub const LSI_FREQ: u32 = 32_000;
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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HSE(Hertz),
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HSI16(HSI16Prescaler),
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2021-07-30 22:48:13 +02:00
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LSI,
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}
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2021-08-31 07:48:22 +02:00
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#[derive(Clone, Copy)]
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pub enum HSI16Prescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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Div32,
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Div64,
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Div128,
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}
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impl Into<u8> for HSI16Prescaler {
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fn into(self) -> u8 {
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match self {
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HSI16Prescaler::NotDivided => 0x00,
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HSI16Prescaler::Div2 => 0x01,
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HSI16Prescaler::Div4 => 0x02,
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HSI16Prescaler::Div8 => 0x03,
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HSI16Prescaler::Div16 => 0x04,
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HSI16Prescaler::Div32 => 0x05,
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HSI16Prescaler::Div64 => 0x06,
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HSI16Prescaler::Div128 => 0x07,
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}
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}
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}
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2021-11-28 16:46:08 +01:00
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/// AHB prescaler
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#[derive(Clone, Copy, PartialEq)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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2021-07-30 22:48:13 +02:00
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impl Into<u8> for APBPrescaler {
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fn into(self) -> u8 {
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match self {
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APBPrescaler::NotDivided => 1,
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APBPrescaler::Div2 => 0x04,
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APBPrescaler::Div4 => 0x05,
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APBPrescaler::Div8 => 0x06,
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APBPrescaler::Div16 => 0x07,
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}
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}
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}
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impl Into<u8> for AHBPrescaler {
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fn into(self) -> u8 {
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match self {
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AHBPrescaler::NotDivided => 1,
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AHBPrescaler::Div2 => 0x08,
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AHBPrescaler::Div4 => 0x09,
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AHBPrescaler::Div8 => 0x0a,
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AHBPrescaler::Div16 => 0x0b,
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AHBPrescaler::Div64 => 0x0c,
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AHBPrescaler::Div128 => 0x0d,
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AHBPrescaler::Div256 => 0x0e,
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AHBPrescaler::Div512 => 0x0f,
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}
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}
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}
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/// Clocks configutation
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pub struct Config {
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mux: ClockSrc,
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ahb_pre: AHBPrescaler,
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apb_pre: APBPrescaler,
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low_power_run: bool,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::HSI16(HSI16Prescaler::NotDivided),
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ahb_pre: AHBPrescaler::NotDivided,
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apb_pre: APBPrescaler::NotDivided,
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low_power_run: false,
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}
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}
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}
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impl Config {
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#[inline]
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pub fn clock_src(mut self, mux: ClockSrc) -> Self {
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self.mux = mux;
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self
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}
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#[inline]
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pub fn ahb_pre(mut self, pre: AHBPrescaler) -> Self {
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self.ahb_pre = pre;
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self
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}
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#[inline]
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pub fn apb_pre(mut self, pre: APBPrescaler) -> Self {
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self.apb_pre = pre;
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self
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}
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2021-08-31 07:51:49 +02:00
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#[inline]
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pub fn low_power_run(mut self, on: bool) -> Self {
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self.low_power_run = on;
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self
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}
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2021-07-30 22:48:13 +02:00
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}
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/// RCC peripheral
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pub struct Rcc<'d> {
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_rb: peripherals::RCC,
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phantom: PhantomData<&'d mut peripherals::RCC>,
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}
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impl<'d> Rcc<'d> {
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pub fn new(rcc: impl Unborrow<Target = peripherals::RCC> + 'd) -> Self {
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unborrow!(rcc);
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Self {
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_rb: rcc,
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phantom: PhantomData,
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}
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}
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// Safety: RCC init must have been called
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pub fn clocks(&self) -> &'static Clocks {
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unsafe { get_freqs() }
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}
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}
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/// Extension trait that freezes the `RCC` peripheral with provided clocks configuration
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pub trait RccExt {
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fn freeze(self, config: Config) -> Clocks;
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}
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impl RccExt for RCC {
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#[inline]
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fn freeze(self, cfgr: Config) -> Clocks {
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let rcc = pac::RCC;
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let (sys_clk, sw) = match cfgr.mux {
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2021-08-31 07:48:22 +02:00
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ClockSrc::HSI16(div) => {
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// Enable HSI16
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let div: u8 = div.into();
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unsafe {
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rcc.cr().write(|w| {
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w.set_hsidiv(div);
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w.set_hsion(true)
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});
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2021-07-30 22:48:13 +02:00
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while !rcc.cr().read().hsirdy() {}
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}
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2021-08-31 07:48:22 +02:00
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(HSI_FREQ >> div, 0x00)
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
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unsafe {
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rcc.cr().write(|w| w.set_hseon(true));
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while !rcc.cr().read().hserdy() {}
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}
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(freq.0, 0x01)
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}
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ClockSrc::LSI => {
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// Enable LSI
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unsafe {
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rcc.csr().write(|w| w.set_lsion(true));
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while !rcc.csr().read().lsirdy() {}
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}
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(LSI_FREQ, 0x03)
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}
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};
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unsafe {
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rcc.cfgr().modify(|w| {
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w.set_sw(sw.into());
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w.set_hpre(cfgr.ahb_pre.into());
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w.set_ppre(cfgr.apb_pre.into());
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});
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}
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let ahb_freq: u32 = match cfgr.ahb_pre {
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AHBPrescaler::NotDivided => sys_clk,
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pre => {
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let pre: u8 = pre.into();
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let pre = 1 << (pre as u32 - 7);
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sys_clk / pre
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}
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};
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let (apb_freq, apb_tim_freq) = match cfgr.apb_pre {
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APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
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pre => {
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let pre: u8 = pre.into();
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let pre: u8 = 1 << (pre - 3);
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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2021-08-31 07:51:49 +02:00
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let pwr = pac::PWR;
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if cfgr.low_power_run {
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assert!(sys_clk.hz() <= 2_000_000.hz());
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unsafe {
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pwr.cr1().modify(|w| w.set_lpr(true));
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}
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}
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2021-07-30 22:48:13 +02:00
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Clocks {
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sys: sys_clk.hz(),
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ahb: ahb_freq.hz(),
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apb: apb_freq.hz(),
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apb_tim: apb_tim_freq.hz(),
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}
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}
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}
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pub unsafe fn init(config: Config) {
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let r = <peripherals::RCC as embassy::util::Steal>::steal();
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let clocks = r.freeze(config);
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set_freqs(clocks);
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}
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