Slave: write Starts working work in progress
This commit is contained in:
anton smeenk
279
examples/stm32g0/src/bin/i2c_slave.rs
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279
examples/stm32g0/src/bin/i2c_slave.rs
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use core::fmt::{self, Write};
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use embassy_executor::Spawner;
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use embassy_stm32::dma::NoDma;
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use embassy_stm32::i2c::I2c;
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use embassy_stm32::pac::i2c::vals;
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use embassy_stm32::time::Hertz;
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use embassy_stm32::usart::UartTx;
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use embassy_stm32::{bind_interrupts, i2c, peripherals, usart};
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use {defmt_rtt as _, panic_probe as _};
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bind_interrupts!(struct Irqs {
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I2C1 => i2c::InterruptHandler<peripherals::I2C1>;
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USART1 => usart::InterruptHandler<peripherals::USART1>;
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});
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macro_rules! checkIsWrite {
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($writer:ident, $direction:ident) => {
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match $direction {
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vals::Dir::WRITE => (),
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_ => {
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write!($writer, "Error incorrect direction {:?}\r", $direction as usize).unwrap();
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continue;
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}
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}
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};
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}
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macro_rules! checkIsRead {
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($writer:ident, $direction:ident) => {
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match $direction {
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vals::Dir::READ => (),
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_ => {
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write!($writer, "Error incorrect direction {:?}\r", $direction as usize).unwrap();
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continue;
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}
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}
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};
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}
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pub struct SerialWriter {
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tx: UartTx<'static, peripherals::USART1, peripherals::DMA1_CH1>,
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}
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impl SerialWriter {
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pub fn new(tx: UartTx<'static, peripherals::USART1, peripherals::DMA1_CH1>) -> Self {
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SerialWriter { tx }
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}
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}
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impl fmt::Write for SerialWriter {
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fn write_str(&mut self, s: &str) -> fmt::Result {
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_ = self.tx.blocking_write(s.as_bytes());
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Ok(())
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}
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}
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let p = embassy_stm32::init(Default::default());
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let uart = usart::Uart::new(
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p.USART1,
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p.PB7,
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p.PB6,
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Irqs,
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p.DMA1_CH1,
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p.DMA1_CH2,
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usart::Config::default(),
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)
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.unwrap();
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let (tx, _rx) = uart.split();
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let mut writer = SerialWriter::new(tx);
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writeln!(
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&mut writer,
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"async i2c slave test. Should be used together with i2c_master test\r"
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)
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.unwrap();
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let mut config = i2c::Config::default();
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config.slave_address_7bits(0x4);
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config.slave_address_2(0x41, vals::Oamsk::MASK4);
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writeln!(&mut writer, "After config:\r",).unwrap();
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let mut i2c = I2c::new(p.I2C1, p.PB8, p.PB9, Irqs, NoDma, NoDma, Hertz(100_000), config);
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writeln!(&mut writer, "After i2c init\r").unwrap();
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let mut buf_64 = [0; 64]; // buffer is longer than master will send: wait for STOP condition
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let mut buf_20 = [0; 20]; // buffer is shorter than master will send: wait for STOP condition
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let mut errors = 0;
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let mut address = 0;
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let mut dir = vals::Dir::READ;
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let mut tcount = 0;
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let mut counter = 0;
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let mut error = Ok((0, vals::Dir::READ, 0));
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// start of the actual test
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i2c.slave_start_listen().unwrap();
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loop {
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counter += 1;
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writeln!(&mut writer, "Loop: {}\r", counter).unwrap();
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for i in 0..buf_20.len() {
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buf_20[i] = 0x61 + (i as u8)
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}
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for i in 0..buf_64.len() {
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buf_64[i] = 0x41 + (i as u8)
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}
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writeln!(&mut writer, "Waiting for master activity\r").unwrap();
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error = Ok((0, vals::Dir::WRITE, 0));
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match i2c.slave_transaction().await {
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Ok((taddr, tdir, tsize)) => {
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address = taddr;
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dir = tdir;
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writeln!(
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&mut writer,
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"Test ok. Address: x{:2x} dir: {:?} size: x{:2x}\r",
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taddr, tdir as u8, tsize
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)
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.unwrap();
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}
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Err(e) => {
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error = Err(e);
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writeln!(&mut writer, "Test failed: Error: {:?}", e).unwrap()
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}
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}
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tcount += 1;
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match address {
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0x41 => {
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// 0x41 good case master write slave read: master does send 20 bytes slave receives 20 bytes
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checkIsWrite!(writer, dir);
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_ = i2c.slave_read_buffer(&mut buf_20, i2c::AddressType::GenericAddress);
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match error {
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Ok(_) => {
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writeln!(&mut writer, "Test 0x41 Ok. send 20 bytes").unwrap();
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print_buffer(&mut writer, &buf_20);
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}
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Err(err) => {
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errors += 1;
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writeln!(&mut writer, "Test 0x41 failed. Error: {:?}\r", err).unwrap()
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}
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};
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}
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0x42 => {
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// 0x42 good case edge case: exact 64 bytes master write slave read:
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checkIsWrite!(writer, dir);
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_ = i2c.slave_read_buffer(&mut buf_64, i2c::AddressType::GenericAddress);
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match error {
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Ok(_) => {
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writeln!(&mut writer, "Test 0x42 Ok. send 64 bytes").unwrap();
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print_buffer(&mut writer, &buf_64);
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}
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Err(err) => {
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errors += 1;
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writeln!(&mut writer, "Test 0x42 failed. Error: {:?}\r", err).unwrap()
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}
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};
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}
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0x43 => {
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// 0x43 bad case master write slave read: master does send more than 64 bytes, slave does NACK
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checkIsWrite!(writer, dir);
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_ = i2c.slave_read_buffer(&mut buf_64, i2c::AddressType::GenericAddress);
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match i2c.slave_read_buffer(&mut buf_64, i2c::AddressType::GenericAddress) {
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Ok(_) => {
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{
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writeln!(&mut writer, "Test 0x43 failed. Expected to fail. with FrameError\r").unwrap()
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};
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}
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Err(err) => {
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errors += 1;
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writeln!(&mut writer, "Test 0x43 Ok Expected error. Error: {:?}\r", err).unwrap()
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}
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};
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}
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0x48 => {
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// 0x48 master read slave write slave did not yet prepare a buffer, master will fail
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checkIsRead!(writer, dir);
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match error {
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Ok(_) => {
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writeln!(&mut writer, "Test 0x48 fail expected to fail: \r").unwrap();
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errors += 1;
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}
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Err(err) => writeln!(&mut writer, "Test 0x48 Ok. Expected error: {:?}\r", err).unwrap(),
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};
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// prepare buffer for next round
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for i in 0..buf_20.len() {
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buf_20[i] = 0x61 + (i as u8)
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}
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_ = i2c.slave_write_buffer(&buf_20, i2c::AddressType::GenericAddress);
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}
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0x49 => {
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// 0x49 master read slave write bad case: master expects 50 does slave does send 20 characters
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checkIsRead!(writer, dir);
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match error {
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Ok(_) => {
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writeln!(&mut writer, "Test 0x49 Ok. master did read 20 bytes").unwrap();
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}
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Err(err) => {
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errors += 1;
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writeln!(&mut writer, "Test 0x49 failed. Error: {:?}\r", err).unwrap()
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}
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};
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// prepare buffer for next round
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for i in 0..buf_20.len() {
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buf_20[i] = 0x41 + (i as u8)
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}
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_ = i2c.slave_write_buffer(&buf_20, i2c::AddressType::GenericAddress);
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}
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0x4A => {
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// 0x4A master read slave write bad case: master expects 64 does slave does prepare 20 characters
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checkIsRead!(writer, dir);
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match error {
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Ok(_) => {
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writeln!(&mut writer, "Test 0x4A failed . Expected an errpr").unwrap();
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}
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Err(err) => {
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errors += 1;
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writeln!(&mut writer, "Test 0x4A ok. Expected errore rror: {:?}\r", err).unwrap()
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}
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}
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_ = i2c.slave_write_buffer(&buf_20, i2c::AddressType::GenericAddress);
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// prepare buffer for next round
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for i in 0..buf_64.len() {
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buf_64[i] = 0x41 + (i as u8)
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}
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_ = i2c.slave_write_buffer(&buf_64, i2c::AddressType::GenericAddress);
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}
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0x4B => {
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// 0x4B master write_read good case each 20 chars
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checkIsRead!(writer, dir);
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match error {
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Ok(_) => {
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writeln!(&mut writer, "Test 0x4B Ok\r").unwrap();
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}
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Err(err) => {
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errors += 1;
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writeln!(&mut writer, "Test 0x4B failed. Error: {:?}\r", err).unwrap()
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}
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};
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let result: [u8; 2] = [tcount, errors];
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_ = i2c.slave_write_buffer(&result, i2c::AddressType::GenericAddress);
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}
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0x4F => {
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checkIsRead!(writer, dir);
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match error {
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Ok(_) => {
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writeln!(&mut writer, "Test 0x4F Result send to master\r").unwrap();
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}
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Err(err) => {
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errors += 1;
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writeln!(&mut writer, "Test 0x4F failed. Error: {:?}\r", err).unwrap()
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}
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};
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writeln!(
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&mut writer,
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"Test finished. nr tests/nr errors: {}/{}!\r",
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tcount, errors
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)
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.unwrap();
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writeln!(&mut writer, "-----\r").unwrap();
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tcount = 0;
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errors = 0;
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}
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_ => (),
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}
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}
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fn print_buffer(writer: &mut SerialWriter, buf: &[u8]) {
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for i in 0..buf.len() {
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write!(writer, " {:2x} ", buf[i]).unwrap();
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}
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writeln!(writer, "\n\r").unwrap()
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}
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}
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