stm32: consolidate crates
This commit is contained in:
xoviat
2
embassy-stm32/src/f4/mod.rs
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2
embassy-stm32/src/f4/mod.rs
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@@ -0,0 +1,2 @@
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pub mod qei;
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pub mod serial;
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91
embassy-stm32/src/f4/qei.rs
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91
embassy-stm32/src/f4/qei.rs
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@@ -0,0 +1,91 @@
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use crate::interrupt;
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use core::future::Future;
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use core::pin::Pin;
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use embassy::traits::qei::WaitForRotate;
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use embedded_hal::Direction;
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use stm32f4xx_hal::pac::TIM2;
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use stm32f4xx_hal::{qei, qei::Pins};
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pub struct Qei<T: Instance, PINS> {
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_qei: qei::Qei<T, PINS>,
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int: T::Interrupt,
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}
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impl<PINS: Pins<TIM2>> Qei<TIM2, PINS> {
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pub fn tim2(tim: TIM2, pins: PINS, interrupt: interrupt::TIM2) -> Self {
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let qei = qei::Qei::tim2(tim, pins);
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let tim = unsafe {
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&mut *(stm32f4xx_hal::stm32::TIM2::ptr()
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as *mut stm32f4xx_hal::stm32::tim2::RegisterBlock)
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};
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/*
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enable qei interrupt
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*/
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tim.dier.write(|w| w.uie().set_bit());
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Qei {
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_qei: qei,
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int: interrupt,
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}
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}
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}
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impl<PINS: Pins<TIM2> + 'static> WaitForRotate for Qei<TIM2, PINS> {
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type RotateFuture<'a> = impl Future<Output = Direction> + 'a;
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fn wait_for_rotate<'a>(
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self: Pin<&'a mut Self>,
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count_down: u16,
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count_up: u16,
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) -> Self::RotateFuture<'a> {
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let s = unsafe { self.get_unchecked_mut() };
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let tim = unsafe {
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&mut *(stm32f4xx_hal::stm32::TIM2::ptr()
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as *mut stm32f4xx_hal::stm32::tim2::RegisterBlock)
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};
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/*
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the interrupt will be reached at zero or the max count
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write the total range to the qei.
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*/
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tim.arr
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.write(|w| unsafe { w.bits((count_down + count_up) as u32) });
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/*
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set timer to the correct value in the range
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*/
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tim.cnt.write(|w| unsafe { w.bits(count_down as u32) });
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/*
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clear interrupt flag
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*/
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tim.sr.write(|w| w.uif().clear_bit());
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async move {
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embassy::util::InterruptFuture::new(&mut s.int).await;
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if tim.cnt.read().bits() == 0 {
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Direction::Downcounting
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} else if tim.cnt.read() == count_down + count_up {
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Direction::Upcounting
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} else {
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panic!("unexpected value")
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}
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}
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}
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}
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mod sealed {
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pub trait Sealed {}
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}
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pub trait Instance: sealed::Sealed {
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type Interrupt: interrupt::Interrupt;
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}
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impl sealed::Sealed for TIM2 {}
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impl Instance for TIM2 {
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type Interrupt = interrupt::TIM2;
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}
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364
embassy-stm32/src/f4/serial.rs
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364
embassy-stm32/src/f4/serial.rs
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@@ -0,0 +1,364 @@
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//! Async Serial.
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use core::future::Future;
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use core::marker::PhantomData;
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use core::pin::Pin;
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use embassy::interrupt::Interrupt;
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use embassy::traits::uart::{Error, Read, ReadUntilIdle, Write};
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use embassy::util::InterruptFuture;
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use futures::{select_biased, FutureExt};
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use crate::hal::{
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dma,
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dma::config::DmaConfig,
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dma::traits::{Channel, DMASet, PeriAddress, Stream},
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dma::{MemoryToPeripheral, PeripheralToMemory, Transfer},
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rcc::Clocks,
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serial,
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serial::config::{Config as SerialConfig, DmaConfig as SerialDmaConfig},
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serial::{Event as SerialEvent, Pins},
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};
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use crate::interrupt;
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use crate::pac;
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/// Interface to the Serial peripheral
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pub struct Serial<
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USART: PeriAddress<MemSize = u8> + WithInterrupt,
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TSTREAM: Stream + WithInterrupt,
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RSTREAM: Stream + WithInterrupt,
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CHANNEL: Channel,
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> {
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tx_stream: Option<TSTREAM>,
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rx_stream: Option<RSTREAM>,
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usart: Option<USART>,
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tx_int: TSTREAM::Interrupt,
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rx_int: RSTREAM::Interrupt,
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usart_int: USART::Interrupt,
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channel: PhantomData<CHANNEL>,
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}
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// static mut INSTANCE: *const Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> = ptr::null_mut();
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impl<USART, TSTREAM, RSTREAM, CHANNEL> Serial<USART, TSTREAM, RSTREAM, CHANNEL>
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where
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USART: serial::Instance
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+ PeriAddress<MemSize = u8>
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+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
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+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
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+ WithInterrupt,
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TSTREAM: Stream + WithInterrupt,
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RSTREAM: Stream + WithInterrupt,
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CHANNEL: Channel,
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{
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// Leaking futures is forbidden!
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pub unsafe fn new<PINS>(
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usart: USART,
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streams: (TSTREAM, RSTREAM),
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pins: PINS,
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tx_int: TSTREAM::Interrupt,
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rx_int: RSTREAM::Interrupt,
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usart_int: USART::Interrupt,
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mut config: SerialConfig,
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clocks: Clocks,
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) -> Self
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where
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PINS: Pins<USART>,
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{
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config.dma = SerialDmaConfig::TxRx;
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let (usart, _) = serial::Serial::new(usart, pins, config, clocks)
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.unwrap()
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.release();
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let (tx_stream, rx_stream) = streams;
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Serial {
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tx_stream: Some(tx_stream),
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rx_stream: Some(rx_stream),
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usart: Some(usart),
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tx_int: tx_int,
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rx_int: rx_int,
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usart_int: usart_int,
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channel: PhantomData,
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}
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}
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}
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impl<USART, TSTREAM, RSTREAM, CHANNEL> Read for Serial<USART, TSTREAM, RSTREAM, CHANNEL>
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where
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USART: serial::Instance
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+ PeriAddress<MemSize = u8>
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+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
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+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
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+ WithInterrupt
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+ 'static,
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TSTREAM: Stream + WithInterrupt + 'static,
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RSTREAM: Stream + WithInterrupt + 'static,
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CHANNEL: Channel + 'static,
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{
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type ReadFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
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/// Receives serial data.
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///
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/// The future is pending until the buffer is completely filled.
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fn read<'a>(self: Pin<&'a mut Self>, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
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let this = unsafe { self.get_unchecked_mut() };
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let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
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async move {
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let rx_stream = this.rx_stream.take().unwrap();
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let usart = this.usart.take().unwrap();
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let mut rx_transfer = Transfer::init(
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rx_stream,
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usart,
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static_buf,
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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);
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let fut = InterruptFuture::new(&mut this.rx_int);
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rx_transfer.start(|_usart| {});
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fut.await;
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let (rx_stream, usart, _, _) = rx_transfer.free();
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this.rx_stream.replace(rx_stream);
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this.usart.replace(usart);
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Ok(())
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}
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}
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}
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impl<USART, TSTREAM, RSTREAM, CHANNEL> Write for Serial<USART, TSTREAM, RSTREAM, CHANNEL>
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where
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USART: serial::Instance
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+ PeriAddress<MemSize = u8>
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+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
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+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
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+ WithInterrupt
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+ 'static,
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TSTREAM: Stream + WithInterrupt + 'static,
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RSTREAM: Stream + WithInterrupt + 'static,
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CHANNEL: Channel + 'static,
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{
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type WriteFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
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/// Sends serial data.
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fn write<'a>(self: Pin<&'a mut Self>, buf: &'a [u8]) -> Self::WriteFuture<'a> {
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let this = unsafe { self.get_unchecked_mut() };
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#[allow(mutable_transmutes)]
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let static_buf = unsafe { core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf) };
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async move {
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let tx_stream = this.tx_stream.take().unwrap();
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let usart = this.usart.take().unwrap();
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let mut tx_transfer = Transfer::init(
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tx_stream,
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usart,
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static_buf,
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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);
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let fut = InterruptFuture::new(&mut this.tx_int);
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tx_transfer.start(|_usart| {});
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fut.await;
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let (tx_stream, usart, _buf, _) = tx_transfer.free();
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this.tx_stream.replace(tx_stream);
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this.usart.replace(usart);
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Ok(())
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}
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}
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}
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impl<USART, TSTREAM, RSTREAM, CHANNEL> ReadUntilIdle for Serial<USART, TSTREAM, RSTREAM, CHANNEL>
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where
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USART: serial::Instance
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+ PeriAddress<MemSize = u8>
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+ DMASet<TSTREAM, CHANNEL, MemoryToPeripheral>
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+ DMASet<RSTREAM, CHANNEL, PeripheralToMemory>
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+ WithInterrupt
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+ 'static,
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TSTREAM: Stream + WithInterrupt + 'static,
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RSTREAM: Stream + WithInterrupt + 'static,
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CHANNEL: Channel + 'static,
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{
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type ReadUntilIdleFuture<'a> = impl Future<Output = Result<usize, Error>> + 'a;
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/// Receives serial data.
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///
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/// The future is pending until either the buffer is completely full, or the RX line falls idle after receiving some data.
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///
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/// Returns the number of bytes read.
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fn read_until_idle<'a>(
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self: Pin<&'a mut Self>,
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buf: &'a mut [u8],
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) -> Self::ReadUntilIdleFuture<'a> {
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let this = unsafe { self.get_unchecked_mut() };
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let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
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async move {
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let rx_stream = this.rx_stream.take().unwrap();
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let usart = this.usart.take().unwrap();
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unsafe {
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/* __HAL_UART_ENABLE_IT(&uart->UartHandle, UART_IT_IDLE); */
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(*USART::ptr()).cr1.modify(|_, w| w.idleie().set_bit());
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/* __HAL_UART_CLEAR_IDLEFLAG(&uart->UartHandle); */
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(*USART::ptr()).sr.read();
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(*USART::ptr()).dr.read();
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};
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let mut rx_transfer = Transfer::init(
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rx_stream,
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usart,
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static_buf,
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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);
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let total_bytes = RSTREAM::get_number_of_transfers() as usize;
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let fut = InterruptFuture::new(&mut this.rx_int);
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let fut_idle = InterruptFuture::new(&mut this.usart_int);
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rx_transfer.start(|_usart| {});
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futures::future::select(fut, fut_idle).await;
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let (rx_stream, usart, _, _) = rx_transfer.free();
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let remaining_bytes = RSTREAM::get_number_of_transfers() as usize;
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unsafe {
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(*USART::ptr()).cr1.modify(|_, w| w.idleie().clear_bit());
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}
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this.rx_stream.replace(rx_stream);
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this.usart.replace(usart);
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Ok(total_bytes - remaining_bytes)
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}
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}
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}
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mod private {
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pub trait Sealed {}
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}
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pub trait WithInterrupt: private::Sealed {
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type Interrupt: Interrupt;
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}
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macro_rules! dma {
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($($PER:ident => ($dma:ident, $stream:ident),)+) => {
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$(
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impl private::Sealed for dma::$stream<pac::$dma> {}
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impl WithInterrupt for dma::$stream<pac::$dma> {
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type Interrupt = interrupt::$PER;
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}
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)+
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}
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}
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macro_rules! usart {
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($($PER:ident => ($usart:ident),)+) => {
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$(
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impl private::Sealed for pac::$usart {}
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impl WithInterrupt for pac::$usart {
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type Interrupt = interrupt::$PER;
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}
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)+
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}
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}
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dma! {
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DMA2_STREAM0 => (DMA2, Stream0),
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DMA2_STREAM1 => (DMA2, Stream1),
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DMA2_STREAM2 => (DMA2, Stream2),
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DMA2_STREAM3 => (DMA2, Stream3),
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DMA2_STREAM4 => (DMA2, Stream4),
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DMA2_STREAM5 => (DMA2, Stream5),
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DMA2_STREAM6 => (DMA2, Stream6),
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DMA2_STREAM7 => (DMA2, Stream7),
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DMA1_STREAM0 => (DMA1, Stream0),
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DMA1_STREAM1 => (DMA1, Stream1),
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DMA1_STREAM2 => (DMA1, Stream2),
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DMA1_STREAM3 => (DMA1, Stream3),
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DMA1_STREAM4 => (DMA1, Stream4),
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DMA1_STREAM5 => (DMA1, Stream5),
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DMA1_STREAM6 => (DMA1, Stream6),
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}
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#[cfg(any(feature = "stm32f401", feature = "stm32f410", feature = "stm32f411",))]
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usart! {
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USART1 => (USART1),
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USART2 => (USART2),
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USART6 => (USART6),
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}
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#[cfg(any(feature = "stm32f405", feature = "stm32f407"))]
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usart! {
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USART1 => (USART1),
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USART2 => (USART2),
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USART3 => (USART3),
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USART6 => (USART6),
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UART4 => (UART4),
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UART5 => (UART5),
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}
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#[cfg(feature = "stm32f412")]
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usart! {
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USART1 => (USART1),
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USART2 => (USART2),
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USART3 => (USART3),
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USART6 => (USART6),
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}
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#[cfg(feature = "stm32f413")]
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usart! {
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USART1 => (USART1),
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USART2 => (USART2),
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USART3 => (USART3),
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USART6 => (USART6),
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USART7 => (USART7),
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USART8 => (USART8),
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UART5 => (UART5),
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UART9 => (UART9),
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UART10 => (UART10),
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}
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#[cfg(any(
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feature = "stm32f427",
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feature = "stm32f429",
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feature = "stm32f446",
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feature = "stm32f469"
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))]
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usart! {
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USART1 => (USART1),
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USART2 => (USART2),
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USART3 => (USART3),
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USART6 => (USART6),
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UART4 => (UART4),
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UART5 => (UART5),
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// UART7 => (UART7),
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// UART8 => (UART8),
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}
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