Initial support for STM32F767ZI.
This commit is contained in:
Matous Hybl
committed by
Dario Nieuwenhuis
Dario Nieuwenhuis
parent
7cb34760c4
commit
015cad84dd
@ -378,6 +378,94 @@ stm32f479vg = [ "stm32-metapac/stm32f479vg" ]
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stm32f479vi = [ "stm32-metapac/stm32f479vi" ]
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stm32f479zg = [ "stm32-metapac/stm32f479zg" ]
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stm32f479zi = [ "stm32-metapac/stm32f479zi" ]
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stm32f722ic = [ "stm32-metapac/stm32f722ic" ]
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stm32f722ie = [ "stm32-metapac/stm32f722ie" ]
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stm32f722rc = [ "stm32-metapac/stm32f722rc" ]
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stm32f722re = [ "stm32-metapac/stm32f722re" ]
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stm32f722vc = [ "stm32-metapac/stm32f722vc" ]
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stm32f722ve = [ "stm32-metapac/stm32f722ve" ]
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stm32f722zc = [ "stm32-metapac/stm32f722zc" ]
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stm32f722ze = [ "stm32-metapac/stm32f722ze" ]
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stm32f723ic = [ "stm32-metapac/stm32f723ic" ]
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stm32f723ie = [ "stm32-metapac/stm32f723ie" ]
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stm32f723vc = [ "stm32-metapac/stm32f723vc" ]
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stm32f723ve = [ "stm32-metapac/stm32f723ve" ]
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stm32f723zc = [ "stm32-metapac/stm32f723zc" ]
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stm32f723ze = [ "stm32-metapac/stm32f723ze" ]
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stm32f730i8 = [ "stm32-metapac/stm32f730i8" ]
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stm32f730r8 = [ "stm32-metapac/stm32f730r8" ]
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stm32f730v8 = [ "stm32-metapac/stm32f730v8" ]
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stm32f730z8 = [ "stm32-metapac/stm32f730z8" ]
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stm32f732ie = [ "stm32-metapac/stm32f732ie" ]
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stm32f732re = [ "stm32-metapac/stm32f732re" ]
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stm32f732ve = [ "stm32-metapac/stm32f732ve" ]
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stm32f732ze = [ "stm32-metapac/stm32f732ze" ]
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stm32f733ie = [ "stm32-metapac/stm32f733ie" ]
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stm32f733ve = [ "stm32-metapac/stm32f733ve" ]
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stm32f733ze = [ "stm32-metapac/stm32f733ze" ]
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stm32f745ie = [ "stm32-metapac/stm32f745ie" ]
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stm32f745ig = [ "stm32-metapac/stm32f745ig" ]
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stm32f745ve = [ "stm32-metapac/stm32f745ve" ]
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stm32f745vg = [ "stm32-metapac/stm32f745vg" ]
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stm32f745ze = [ "stm32-metapac/stm32f745ze" ]
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stm32f745zg = [ "stm32-metapac/stm32f745zg" ]
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stm32f746be = [ "stm32-metapac/stm32f746be" ]
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stm32f746bg = [ "stm32-metapac/stm32f746bg" ]
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stm32f746ie = [ "stm32-metapac/stm32f746ie" ]
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stm32f746ig = [ "stm32-metapac/stm32f746ig" ]
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stm32f746ne = [ "stm32-metapac/stm32f746ne" ]
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stm32f746ng = [ "stm32-metapac/stm32f746ng" ]
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stm32f746ve = [ "stm32-metapac/stm32f746ve" ]
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stm32f746vg = [ "stm32-metapac/stm32f746vg" ]
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stm32f746ze = [ "stm32-metapac/stm32f746ze" ]
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stm32f746zg = [ "stm32-metapac/stm32f746zg" ]
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stm32f750n8 = [ "stm32-metapac/stm32f750n8" ]
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stm32f750v8 = [ "stm32-metapac/stm32f750v8" ]
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stm32f750z8 = [ "stm32-metapac/stm32f750z8" ]
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stm32f756bg = [ "stm32-metapac/stm32f756bg" ]
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stm32f756ig = [ "stm32-metapac/stm32f756ig" ]
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stm32f756ng = [ "stm32-metapac/stm32f756ng" ]
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stm32f756vg = [ "stm32-metapac/stm32f756vg" ]
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stm32f756zg = [ "stm32-metapac/stm32f756zg" ]
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stm32f765bg = [ "stm32-metapac/stm32f765bg" ]
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stm32f765bi = [ "stm32-metapac/stm32f765bi" ]
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stm32f765ig = [ "stm32-metapac/stm32f765ig" ]
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stm32f765ii = [ "stm32-metapac/stm32f765ii" ]
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stm32f765ng = [ "stm32-metapac/stm32f765ng" ]
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stm32f765ni = [ "stm32-metapac/stm32f765ni" ]
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stm32f765vg = [ "stm32-metapac/stm32f765vg" ]
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stm32f765vi = [ "stm32-metapac/stm32f765vi" ]
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stm32f765zg = [ "stm32-metapac/stm32f765zg" ]
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stm32f765zi = [ "stm32-metapac/stm32f765zi" ]
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stm32f767bg = [ "stm32-metapac/stm32f767bg" ]
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stm32f767bi = [ "stm32-metapac/stm32f767bi" ]
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stm32f767ig = [ "stm32-metapac/stm32f767ig" ]
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stm32f767ii = [ "stm32-metapac/stm32f767ii" ]
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stm32f767ng = [ "stm32-metapac/stm32f767ng" ]
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stm32f767ni = [ "stm32-metapac/stm32f767ni" ]
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stm32f767vg = [ "stm32-metapac/stm32f767vg" ]
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stm32f767vi = [ "stm32-metapac/stm32f767vi" ]
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stm32f767zg = [ "stm32-metapac/stm32f767zg" ]
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stm32f767zi = [ "stm32-metapac/stm32f767zi" ]
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stm32f768ai = [ "stm32-metapac/stm32f768ai" ]
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stm32f769ag = [ "stm32-metapac/stm32f769ag" ]
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stm32f769ai = [ "stm32-metapac/stm32f769ai" ]
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stm32f769bg = [ "stm32-metapac/stm32f769bg" ]
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stm32f769bi = [ "stm32-metapac/stm32f769bi" ]
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stm32f769ig = [ "stm32-metapac/stm32f769ig" ]
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stm32f769ii = [ "stm32-metapac/stm32f769ii" ]
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stm32f769ng = [ "stm32-metapac/stm32f769ng" ]
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stm32f769ni = [ "stm32-metapac/stm32f769ni" ]
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stm32f777bi = [ "stm32-metapac/stm32f777bi" ]
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stm32f777ii = [ "stm32-metapac/stm32f777ii" ]
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stm32f777ni = [ "stm32-metapac/stm32f777ni" ]
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stm32f777vi = [ "stm32-metapac/stm32f777vi" ]
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stm32f777zi = [ "stm32-metapac/stm32f777zi" ]
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stm32f778ai = [ "stm32-metapac/stm32f778ai" ]
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stm32f779ai = [ "stm32-metapac/stm32f779ai" ]
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stm32f779bi = [ "stm32-metapac/stm32f779bi" ]
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stm32f779ii = [ "stm32-metapac/stm32f779ii" ]
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stm32f779ni = [ "stm32-metapac/stm32f779ni" ]
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stm32g030c6 = [ "stm32-metapac/stm32g030c6" ]
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stm32g030c8 = [ "stm32-metapac/stm32g030c8" ]
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stm32g030f6 = [ "stm32-metapac/stm32g030f6" ]
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@ -1,6 +1,7 @@
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#![macro_use]
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#[cfg_attr(adc_v3, path = "v3.rs")]
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#[cfg_attr(adc_v2, path = "v2.rs")]
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#[cfg_attr(adc_g0, path = "v3.rs")]
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mod _version;
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1
embassy-stm32/src/adc/v2.rs
Normal file
1
embassy-stm32/src/adc/v2.rs
Normal file
@ -0,0 +1 @@
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@ -119,7 +119,7 @@ crate::pac::peripherals!(
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unsafe impl bxcan::MasterInstance for peripherals::CAN1 {}
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};
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(can, CAN3) => {
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unsafe impl bxcan::FilterOwner for peripherals::$inst {
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unsafe impl bxcan::FilterOwner for peripherals::CAN3 {
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const NUM_FILTER_BANKS: u8 = 14;
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}
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};
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@ -1,5 +1,6 @@
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#![macro_use]
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#[cfg_attr(dac_v1, path = "v1.rs")]
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#[cfg_attr(dac_v2, path = "v2.rs")]
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mod _version;
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use crate::gpio::NoPin;
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1
embassy-stm32/src/dac/v1.rs
Normal file
1
embassy-stm32/src/dac/v1.rs
Normal file
@ -0,0 +1 @@
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1
embassy-stm32/src/pwr/f7.rs
Normal file
1
embassy-stm32/src/pwr/f7.rs
Normal file
@ -0,0 +1 @@
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@ -1,5 +1,6 @@
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#[cfg_attr(any(pwr_h7, pwr_h7smps), path = "h7.rs")]
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#[cfg_attr(pwr_f4, path = "f4.rs")]
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#[cfg_attr(pwr_f7, path = "f7.rs")]
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#[cfg_attr(pwr_wl5, path = "wl5.rs")]
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#[cfg_attr(pwr_g0, path = "g0.rs")]
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#[cfg_attr(pwr_l1, path = "l1.rs")]
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19
embassy-stm32/src/rcc/f7/max.rs
Normal file
19
embassy-stm32/src/rcc/f7/max.rs
Normal file
@ -0,0 +1,19 @@
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pub(crate) const HSE_OSC_MIN: u32 = 4_000_000;
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pub(crate) const HSE_OSC_MAX: u32 = 26_000_000;
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pub(crate) const HSE_BYPASS_MIN: u32 = 1_000_000;
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pub(crate) const HSE_BYPASS_MAX: u32 = 50_000_000;
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pub(crate) const HCLK_MAX: u32 = 216_000_000;
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pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 180_000_000;
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pub(crate) const SYSCLK_MIN: u32 = 12_500_000;
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pub(crate) const SYSCLK_MAX: u32 = 216_000_000;
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pub(crate) const PCLK1_MIN: u32 = SYSCLK_MIN;
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pub(crate) const PCLK1_MAX: u32 = SYSCLK_MAX / 4;
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pub(crate) const PCLK2_MIN: u32 = SYSCLK_MIN;
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pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
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pub(crate) const PLL_48_CLK: u32 = 48_000_000;
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pub(crate) const PLL_48_TOLERANCE: u32 = 120_000;
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347
embassy-stm32/src/rcc/f7/mod.rs
Normal file
347
embassy-stm32/src/rcc/f7/mod.rs
Normal file
@ -0,0 +1,347 @@
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mod max;
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use crate::pac::{FLASH, PWR, RCC};
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use crate::peripherals;
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use crate::rcc::{get_freqs, set_freqs, Clocks};
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use crate::time::Hertz;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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const HSI: u32 = 16_000_000;
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#[non_exhaustive]
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#[derive(Default)]
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pub struct Config {
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub hclk: Option<Hertz>,
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pub sys_ck: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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pub pll48: bool,
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}
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/// RCC peripheral
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pub struct Rcc<'d> {
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config: Config,
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phantom: PhantomData<&'d mut peripherals::RCC>,
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}
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impl<'d> Rcc<'d> {
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pub fn new(_rcc: impl Unborrow<Target = peripherals::RCC> + 'd, config: Config) -> Self {
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if let Some(hse) = config.hse {
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if config.bypass_hse {
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assert!((max::HSE_BYPASS_MIN..=max::HSE_BYPASS_MAX).contains(&hse.0));
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} else {
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assert!((max::HSE_OSC_MIN..=max::HSE_OSC_MAX).contains(&hse.0));
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}
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}
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Self {
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config,
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phantom: PhantomData,
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}
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}
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fn freeze(mut self) -> Clocks {
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use super::sealed::RccPeripheral;
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use crate::pac::pwr::vals::Vos;
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use crate::pac::rcc::vals::{Hpre, Hsebyp, Ppre, Sw};
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let base_clock = self.config.hse.map(|hse| hse.0).unwrap_or(HSI);
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let sysclk = self.config.sys_ck.map(|sys| sys.0).unwrap_or(base_clock);
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let sysclk_on_pll = sysclk != base_clock;
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assert!((max::SYSCLK_MIN..=max::SYSCLK_MAX).contains(&sysclk));
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let plls = self.setup_pll(
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base_clock,
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self.config.hse.is_some(),
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if sysclk_on_pll { Some(sysclk) } else { None },
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self.config.pll48,
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);
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if self.config.pll48 {
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assert!(
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// USB specification allows +-0.25%
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plls.pll48clk
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.map(|freq| (max::PLL_48_CLK as i32 - freq as i32).abs()
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<= max::PLL_48_TOLERANCE as i32)
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.unwrap_or(false)
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);
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}
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let sysclk = if sysclk_on_pll {
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unwrap!(plls.pllsysclk)
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} else {
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sysclk
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};
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// AHB prescaler
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let hclk = self.config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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// Calculate real AHB clock
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let hclk = sysclk / hpre_div;
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assert!(hclk < max::HCLK_MAX);
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let pclk1 = self
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.config
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.pclk1
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK1_MAX, hclk));
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let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
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// Calculate real APB1 clock
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let pclk1 = hclk / ppre1;
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assert!((max::PCLK1_MIN..=max::PCLK1_MAX).contains(&pclk1));
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let pclk2 = self
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.config
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.pclk2
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK2_MAX, hclk));
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let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
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// Calculate real APB2 clock
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let pclk2 = hclk / ppre2;
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assert!((max::PCLK2_MIN..=max::PCLK2_MAX).contains(&pclk2));
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Self::flash_setup(sysclk);
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if self.config.hse.is_some() {
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// NOTE(unsafe) We own the peripheral block
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unsafe {
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RCC.cr().modify(|w| {
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w.set_hsebyp(Hsebyp(self.config.bypass_hse as u8));
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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}
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}
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if plls.use_pll {
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unsafe {
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RCC.cr().modify(|w| w.set_pllon(false));
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// enable PWR and setup VOSScale
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RCC.apb1enr().modify(|w| w.set_pwren(true));
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let vos_scale = if sysclk <= 144_000_000 {
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3
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} else if sysclk <= 168_000_000 {
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2
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} else {
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1
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};
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PWR.cr1().modify(|w| {
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w.set_vos(match vos_scale {
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3 => Vos::SCALE3,
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2 => Vos::SCALE2,
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1 => Vos::SCALE1,
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_ => panic!("Invalid VOS Scale."),
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})
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});
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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if hclk > max::HCLK_OVERDRIVE_FREQUENCY {
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peripherals::PWR::enable();
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PWR.cr1().modify(|w| w.set_oden(true));
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while !PWR.csr1().read().odrdy() {}
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PWR.cr1().modify(|w| w.set_odswen(true));
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while !PWR.csr1().read().odswrdy() {}
|
||||
}
|
||||
|
||||
while !RCC.cr().read().pllrdy() {}
|
||||
}
|
||||
}
|
||||
|
||||
unsafe {
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_ppre2(Ppre(ppre2_bits));
|
||||
w.set_ppre1(Ppre(ppre1_bits));
|
||||
w.set_hpre(hpre_bits);
|
||||
});
|
||||
|
||||
// Wait for the new prescalers to kick in
|
||||
// "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
|
||||
cortex_m::asm::delay(16);
|
||||
|
||||
RCC.cfgr().modify(|w| {
|
||||
w.set_sw(if sysclk_on_pll {
|
||||
Sw::PLL
|
||||
} else if self.config.hse.is_some() {
|
||||
Sw::HSE
|
||||
} else {
|
||||
Sw::HSI
|
||||
})
|
||||
});
|
||||
}
|
||||
|
||||
Clocks {
|
||||
sys: Hertz(sysclk),
|
||||
apb1: Hertz(pclk1),
|
||||
apb2: Hertz(pclk2),
|
||||
|
||||
apb1_tim: Hertz(pclk1 * timer_mul1),
|
||||
apb2_tim: Hertz(pclk2 * timer_mul2),
|
||||
|
||||
ahb1: Hertz(hclk),
|
||||
ahb2: Hertz(hclk),
|
||||
ahb3: Hertz(hclk),
|
||||
}
|
||||
}
|
||||
|
||||
// Safety: RCC init must have been called
|
||||
pub fn clocks(&self) -> &'static Clocks {
|
||||
unsafe { get_freqs() }
|
||||
}
|
||||
|
||||
fn setup_pll(
|
||||
&mut self,
|
||||
pllsrcclk: u32,
|
||||
use_hse: bool,
|
||||
pllsysclk: Option<u32>,
|
||||
pll48clk: bool,
|
||||
) -> PllResults {
|
||||
use crate::pac::rcc::vals::{Pllp, Pllsrc};
|
||||
|
||||
let sysclk = pllsysclk.unwrap_or(pllsrcclk);
|
||||
if pllsysclk.is_none() && !pll48clk {
|
||||
// NOTE(unsafe) We have a mutable borrow to the owner of the RegBlock
|
||||
unsafe {
|
||||
RCC.pllcfgr()
|
||||
.modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
|
||||
}
|
||||
|
||||
return PllResults {
|
||||
use_pll: false,
|
||||
pllsysclk: None,
|
||||
pll48clk: None,
|
||||
};
|
||||
}
|
||||
// Input divisor from PLL source clock, must result to frequency in
|
||||
// the range from 1 to 2 MHz
|
||||
let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
|
||||
let pllm_max = pllsrcclk / 1_000_000;
|
||||
|
||||
// Sysclk output divisor must be one of 2, 4, 6 or 8
|
||||
let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
|
||||
|
||||
let target_freq = if pll48clk {
|
||||
48_000_000
|
||||
} else {
|
||||
sysclk * sysclk_div
|
||||
};
|
||||
|
||||
// Find the lowest pllm value that minimize the difference between
|
||||
// target frequency and the real vco_out frequency.
|
||||
let pllm = unwrap!((pllm_min..=pllm_max).min_by_key(|pllm| {
|
||||
let vco_in = pllsrcclk / pllm;
|
||||
let plln = target_freq / vco_in;
|
||||
target_freq - vco_in * plln
|
||||
}));
|
||||
|
||||
let vco_in = pllsrcclk / pllm;
|
||||
assert!((1_000_000..=2_000_000).contains(&vco_in));
|
||||
|
||||
// Main scaler, must result in >= 100MHz (>= 192MHz for F401)
|
||||
// and <= 432MHz, min 50, max 432
|
||||
let plln = if pll48clk {
|
||||
// try the different valid pllq according to the valid
|
||||
// main scaller values, and take the best
|
||||
let pllq = unwrap!((4..=9).min_by_key(|pllq| {
|
||||
let plln = 48_000_000 * pllq / vco_in;
|
||||
let pll48_diff = 48_000_000 - vco_in * plln / pllq;
|
||||
let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
|
||||
(pll48_diff, sysclk_diff)
|
||||
}));
|
||||
48_000_000 * pllq / vco_in
|
||||
} else {
|
||||
sysclk * sysclk_div / vco_in
|
||||
};
|
||||
|
||||
let pllp = (sysclk_div / 2) - 1;
|
||||
|
||||
let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
|
||||
let real_pll48clk = vco_in * plln / pllq;
|
||||
|
||||
unsafe {
|
||||
RCC.pllcfgr().modify(|w| {
|
||||
w.set_pllm(pllm as u8);
|
||||
w.set_plln(plln as u16);
|
||||
w.set_pllp(Pllp(pllp as u8));
|
||||
w.set_pllq(pllq as u8);
|
||||
w.set_pllsrc(Pllsrc(use_hse as u8));
|
||||
});
|
||||
}
|
||||
|
||||
let real_pllsysclk = vco_in * plln / sysclk_div;
|
||||
|
||||
PllResults {
|
||||
use_pll: true,
|
||||
pllsysclk: Some(real_pllsysclk),
|
||||
pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
|
||||
}
|
||||
}
|
||||
|
||||
fn flash_setup(sysclk: u32) {
|
||||
use crate::pac::flash::vals::Latency;
|
||||
|
||||
// Be conservative with voltage ranges
|
||||
const FLASH_LATENCY_STEP: u32 = 30_000_000;
|
||||
|
||||
critical_section::with(|_| unsafe {
|
||||
FLASH
|
||||
.acr()
|
||||
.modify(|w| w.set_latency(Latency(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
pub unsafe fn init(config: Config) {
|
||||
let r = <peripherals::RCC as embassy::util::Steal>::steal();
|
||||
let clocks = Rcc::new(r, config).freeze();
|
||||
set_freqs(clocks);
|
||||
}
|
||||
|
||||
struct PllResults {
|
||||
use_pll: bool,
|
||||
pllsysclk: Option<u32>,
|
||||
pll48clk: Option<u32>,
|
||||
}
|
||||
@ -30,13 +30,13 @@ pub struct Clocks {
|
||||
#[cfg(any(rcc_l0, rcc_l1, rcc_f0, rcc_f1, rcc_f0x0, rcc_g0))]
|
||||
pub ahb: Hertz,
|
||||
|
||||
#[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb, rcc_wl5))]
|
||||
#[cfg(any(rcc_l4, rcc_f4, rcc_f7, rcc_h7, rcc_wb, rcc_wl5))]
|
||||
pub ahb1: Hertz,
|
||||
|
||||
#[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb, rcc_wl5))]
|
||||
#[cfg(any(rcc_l4, rcc_f4, rcc_f7, rcc_h7, rcc_wb, rcc_wl5))]
|
||||
pub ahb2: Hertz,
|
||||
|
||||
#[cfg(any(rcc_l4, rcc_f4, rcc_h7, rcc_wb, rcc_wl5))]
|
||||
#[cfg(any(rcc_l4, rcc_f4, rcc_f7, rcc_h7, rcc_wb, rcc_wl5))]
|
||||
pub ahb3: Hertz,
|
||||
|
||||
#[cfg(any(rcc_h7))]
|
||||
@ -85,6 +85,9 @@ cfg_if::cfg_if! {
|
||||
} else if #[cfg(rcc_f4)] {
|
||||
mod f4;
|
||||
pub use f4::*;
|
||||
} else if #[cfg(rcc_f7)] {
|
||||
mod f7;
|
||||
pub use f7::*;
|
||||
} else if #[cfg(rcc_wb)] {
|
||||
mod wb;
|
||||
pub use wb::*;
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#![macro_use]
|
||||
|
||||
//#[cfg_attr(sdmmc_v1, path = "v1.rs")]
|
||||
#[cfg_attr(sdmmc_v1, path = "v1.rs")]
|
||||
#[cfg_attr(sdmmc_v2, path = "v2.rs")]
|
||||
mod _version;
|
||||
|
||||
|
||||
1
embassy-stm32/src/sdmmc/v1.rs
Normal file
1
embassy-stm32/src/sdmmc/v1.rs
Normal file
@ -0,0 +1 @@
|
||||
|
||||
Reference in New Issue
Block a user