Merge pull request #17 from xoviat/implement-uart
implement uart on serial interface
This commit is contained in:
commit
0204d4e812
@ -8,6 +8,7 @@
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use cortex_m::singleton;
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use cortex_m_rt::entry;
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use embassy::executor::{task, Executor};
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use embassy::uart::Uart;
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use embassy::util::Forever;
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use embassy_stm32f4::interrupt;
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use embassy_stm32f4::serial;
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@ -27,23 +28,23 @@ async fn run(dp: stm32::Peripherals, cp: cortex_m::Peripherals) {
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.pclk1(24.mhz())
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.freeze();
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let mut serial = serial::Serial::new(
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gpioa.pa9.into_alternate_af7(),
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gpioa.pa10.into_alternate_af7(),
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interrupt::take!(DMA2_STREAM7),
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interrupt::take!(DMA2_STREAM2),
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interrupt::take!(USART1),
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dp.DMA2,
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dp.USART1,
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config::Parity::ParityNone,
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9600.bps(),
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clocks,
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);
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let mut serial = unsafe {
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serial::Serial::new(
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gpioa.pa9.into_alternate_af7(),
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gpioa.pa10.into_alternate_af7(),
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interrupt::take!(DMA2_STREAM7),
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interrupt::take!(DMA2_STREAM2),
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interrupt::take!(USART1),
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dp.DMA2,
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dp.USART1,
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config::Parity::ParityNone,
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9600.bps(),
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clocks,
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)
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};
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let buf = singleton!(: [u8; 30] = [0; 30]).unwrap();
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buf[5] = 0x01;
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serial.send(buf).await;
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}
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@ -10,8 +10,9 @@ use core::sync::atomic::{self, Ordering};
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use core::task::{Context, Poll};
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use embassy::interrupt::OwnedInterrupt;
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use embassy::uart::{Error, Uart};
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use embassy::util::Signal;
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use embedded_dma::{StaticReadBuffer, StaticWriteBuffer, WriteBuffer};
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use embedded_dma::StaticWriteBuffer;
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use crate::hal::dma::config::DmaConfig;
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use crate::hal::dma::traits::{PeriAddress, Stream};
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@ -56,7 +57,8 @@ static STATE: State = State {
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static mut INSTANCE: *const Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> = ptr::null_mut();
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impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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pub fn new(
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// Leaking futures is forbidden!
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pub unsafe fn new(
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txd: PA9<Alternate<AF7>>,
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rxd: PA10<Alternate<AF7>>,
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tx_int: interrupt::DMA2_STREAM7Interrupt,
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@ -135,18 +137,19 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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STATE.rx_int.signal(());
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}
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}
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impl Uart for Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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type SendFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
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type ReceiveFuture<'a> = impl Future<Output = Result<(), Error>> + 'a;
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/// Sends serial data.
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///
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/// `tx_buffer` is marked as static as per `embedded-dma` requirements.
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/// It it safe to use a buffer with a non static lifetime if memory is not
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/// reused until the future has finished.
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pub fn send<'a, B: 'a>(&'a mut self, tx_buffer: B) -> impl Future<Output = ()> + 'a
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where
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B: StaticWriteBuffer<Word = u8>,
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{
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fn send<'a>(&'a mut self, buf: &'a [u8]) -> Self::SendFuture<'a> {
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unsafe { INSTANCE = self };
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#[allow(mutable_transmutes)]
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let static_buf = unsafe { core::mem::transmute::<&'a [u8], &'static mut [u8]>(buf) };
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let tx_stream = self.tx_stream.take().unwrap();
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let usart = self.usart.take().unwrap();
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STATE.tx_int.reset();
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@ -155,7 +158,7 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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let mut tx_transfer = Transfer::init(
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tx_stream,
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usart,
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tx_buffer,
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static_buf,
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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@ -172,6 +175,8 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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let (tx_stream, usart, _buf, _) = tx_transfer.free();
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self.tx_stream.replace(tx_stream);
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self.usart.replace(usart);
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Ok(())
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}
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}
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@ -181,44 +186,32 @@ impl Serial<USART1, Stream7<DMA2>, Stream2<DMA2>> {
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/// A common pattern is to use [`stop()`](ReceiveFuture::stop) to cancel
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/// unfinished transfers after a timeout to prevent lockup when no more data
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/// is incoming.
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///
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/// `rx_buffer` is marked as static as per `embedded-dma` requirements.
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/// It it safe to use a buffer with a non static lifetime if memory is not
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/// reused until the future has finished.
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pub fn receive<'a, B: 'a>(&'a mut self, rx_buffer: B) -> impl Future<Output = B> + 'a
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where
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B: StaticWriteBuffer<Word = u8> + Unpin,
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{
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fn receive<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReceiveFuture<'a> {
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unsafe { INSTANCE = self };
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let static_buf = unsafe { core::mem::transmute::<&'a mut [u8], &'static mut [u8]>(buf) };
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let rx_stream = self.rx_stream.take().unwrap();
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let usart = self.usart.take().unwrap();
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STATE.rx_int.reset();
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async move {
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let mut rx_transfer = Transfer::init(
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rx_stream,
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usart,
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rx_buffer,
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static_buf,
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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);
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self.rx_int.unpend();
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self.rx_int.enable();
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rx_transfer.start(|_usart| {});
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STATE.rx_int.wait().await;
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let (rx_stream, usart, buf, _) = rx_transfer.free();
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let (rx_stream, usart, _, _) = rx_transfer.free();
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self.rx_stream.replace(rx_stream);
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self.usart.replace(usart);
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buf
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Ok(())
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}
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}
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}
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