stm32/dma: simplify impls a bit.
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b316d2620c
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022c4cb739
@ -59,7 +59,7 @@ unsafe fn on_irq() {
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let isr = pac::$dma.isr().read();
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let dman = dma_num!($dma);
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for chn in 0..crate::pac::dma_channels_count!($dma) {
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for chn in 0..pac::dma_channels_count!($dma) {
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let cr = pac::$dma.ch(chn).cr();
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if isr.tcif(chn) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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@ -90,9 +90,8 @@ pac::dma_channels! {
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impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {
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unsafe fn start_write<W: Word>(&mut self, request: Request, buf: &[W], reg_addr: *mut W) {
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low_level_api::reset_status(crate::pac::$dma_peri, $channel_num);
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low_level_api::start_transfer(
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crate::pac::$dma_peri,
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pac::$dma_peri,
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$channel_num,
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#[cfg(any(bdma_v2, dmamux))]
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request,
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@ -112,9 +111,8 @@ pac::dma_channels! {
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unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut W) {
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let buf = [repeated];
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low_level_api::reset_status(crate::pac::$dma_peri, $channel_num);
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low_level_api::start_transfer(
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crate::pac::$dma_peri,
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pac::$dma_peri,
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$channel_num,
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#[cfg(any(bdma_v2, dmamux))]
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request,
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@ -132,9 +130,8 @@ pac::dma_channels! {
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}
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unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *mut W, buf: &mut [W]) {
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low_level_api::reset_status(crate::pac::$dma_peri, $channel_num);
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low_level_api::start_transfer(
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crate::pac::$dma_peri,
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pac::$dma_peri,
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$channel_num,
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#[cfg(any(bdma_v2, dmamux))]
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request,
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@ -152,14 +149,14 @@ pac::dma_channels! {
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}
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fn request_stop(&mut self){
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unsafe {low_level_api::request_stop(crate::pac::$dma_peri, $channel_num);}
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unsafe {low_level_api::request_stop(pac::$dma_peri, $channel_num);}
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}
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fn is_running(&self) -> bool {
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unsafe {low_level_api::is_running(crate::pac::$dma_peri, $channel_num)}
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unsafe {low_level_api::is_running(pac::$dma_peri, $channel_num)}
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}
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fn remaining_transfers(&mut self) -> u16 {
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unsafe {low_level_api::get_remaining_transfers(crate::pac::$dma_peri, $channel_num)}
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unsafe {low_level_api::get_remaining_transfers(pac::$dma_peri, $channel_num)}
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}
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fn set_waker(&mut self, waker: &Waker) {
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@ -198,6 +195,8 @@ mod low_level_api {
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) {
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let ch = dma.ch(channel_number as _);
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reset_status(dma, channel_number);
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#[cfg(dmamux)]
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super::super::dmamux::configure_dmamux(dmamux_regs, dmamux_ch_num, request);
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@ -85,17 +85,15 @@ pac::dma_channels! {
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($channel_peri:ident, $dma_peri:ident, dma, $channel_num:expr, $dmamux:tt) => {
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impl crate::dma::sealed::Channel for crate::peripherals::$channel_peri {
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unsafe fn start_write<W: Word>(&mut self, request: Request, buf: &[W], reg_addr: *mut W) {
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let isrn = $channel_num as usize / 4;
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let isrbit = $channel_num as usize % 4;
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low_level_api::reset_status(&crate::pac::$dma_peri, isrn, isrbit);
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low_level_api::start_transfer(
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pac::$dma_peri,
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$channel_num,
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request,
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vals::Dir::MEMORYTOPERIPHERAL,
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reg_addr as *const u32,
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buf.as_ptr() as *mut u32,
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buf.len(),
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true,
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crate::pac::$dma_peri.st($channel_num as _),
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vals::Size::from(W::bits()),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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@ -106,17 +104,15 @@ pac::dma_channels! {
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unsafe fn start_write_repeated<W: Word>(&mut self, request: Request, repeated: W, count: usize, reg_addr: *mut W) {
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let buf = [repeated];
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let isrn = $channel_num as usize / 4;
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let isrbit = $channel_num as usize % 4;
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low_level_api::reset_status(&crate::pac::$dma_peri, isrn, isrbit);
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low_level_api::start_transfer(
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pac::$dma_peri,
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$channel_num,
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request,
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vals::Dir::MEMORYTOPERIPHERAL,
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reg_addr as *const u32,
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buf.as_ptr() as *mut u32,
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count,
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false,
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crate::pac::$dma_peri.st($channel_num as _),
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vals::Size::from(W::bits()),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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@ -126,17 +122,15 @@ pac::dma_channels! {
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}
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unsafe fn start_read<W: Word>(&mut self, request: Request, reg_addr: *mut W, buf: &mut [W]) {
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let isrn = $channel_num as usize / 4;
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let isrbit = $channel_num as usize % 4;
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low_level_api::reset_status(&crate::pac::$dma_peri, isrn, isrbit);
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low_level_api::start_transfer(
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pac::$dma_peri,
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$channel_num,
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request,
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vals::Dir::PERIPHERALTOMEMORY,
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reg_addr as *const u32,
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buf.as_ptr() as *mut u32,
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buf.len(),
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true,
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crate::pac::$dma_peri.st($channel_num as _),
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vals::Size::from(W::bits()),
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#[cfg(dmamux)]
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<Self as super::dmamux::sealed::MuxChannel>::DMAMUX_REGS,
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@ -146,15 +140,15 @@ pac::dma_channels! {
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}
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fn request_stop(&mut self) {
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unsafe {low_level_api::request_stop(&crate::pac::$dma_peri, $channel_num);}
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unsafe {low_level_api::request_stop(pac::$dma_peri, $channel_num);}
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}
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fn is_running(&self) -> bool {
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unsafe {low_level_api::is_running(&crate::pac::$dma_peri, $channel_num)}
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unsafe {low_level_api::is_running(pac::$dma_peri, $channel_num)}
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}
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fn remaining_transfers(&mut self) -> u16 {
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unsafe {low_level_api::get_remaining_transfers(&crate::pac::$dma_peri, $channel_num)}
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unsafe {low_level_api::get_remaining_transfers(pac::$dma_peri, $channel_num)}
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}
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fn set_waker(&mut self, waker: &Waker) {
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@ -179,13 +173,14 @@ mod low_level_api {
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use super::*;
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pub unsafe fn start_transfer(
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dma: pac::dma::Dma,
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channel_number: u8,
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request: Request,
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dir: vals::Dir,
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peri_addr: *const u32,
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mem_addr: *mut u32,
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mem_len: usize,
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incr_mem: bool,
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ch: crate::pac::dma::St,
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data_size: vals::Size,
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#[cfg(dmamux)] dmamux_regs: pac::dmamux::Dmamux,
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#[cfg(dmamux)] dmamux_ch_num: u8,
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@ -196,6 +191,9 @@ mod low_level_api {
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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reset_status(dma, channel_number);
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let ch = dma.st(channel_number as _);
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ch.par().write_value(peri_addr as u32);
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ch.m0ar().write_value(mem_addr as u32);
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ch.ndtr().write_value(regs::Ndtr(mem_len as _));
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@ -223,34 +221,31 @@ mod low_level_api {
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}
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/// Stops the DMA channel.
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pub unsafe fn request_stop(dma: &pac::dma::Dma, channel_number: u8) {
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// Reset status
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let isrn = channel_number as usize / 4;
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let isrbit = channel_number as usize % 4;
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reset_status(dma, isrn, isrbit);
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pub unsafe fn request_stop(dma: pac::dma::Dma, channel_number: u8) {
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// get a handle on the channel itself
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let ch = dma.st(channel_number as _);
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// Disable the channel and interrupts with the default value.
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ch.cr().write(|_| ());
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_tcie(true);
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});
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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}
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/// Gets the running status of the channel
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pub unsafe fn is_running(dma: &pac::dma::Dma, ch: u8) -> bool {
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pub unsafe fn is_running(dma: pac::dma::Dma, ch: u8) -> bool {
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// get a handle on the channel itself
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let ch = dma.st(ch as _);
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// Wait for the transfer to complete when it was ongoing.
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// Get whether it's enabled (running)
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ch.cr().read().en()
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}
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/// Gets the total remaining transfers for the channel
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/// Note: this will be zero for transfers that completed without cancellation.
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pub unsafe fn get_remaining_transfers(dma: &pac::dma::Dma, ch: u8) -> u16 {
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pub unsafe fn get_remaining_transfers(dma: pac::dma::Dma, ch: u8) -> u16 {
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// get a handle on the channel itself
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let ch = dma.st(ch as _);
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// read the remaining transfer count. If this is zero, the transfer completed fully.
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@ -262,7 +257,10 @@ mod low_level_api {
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STATE.ch_wakers[state_number].register(waker);
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}
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pub unsafe fn reset_status(dma: &crate::pac::dma::Dma, isrn: usize, isrbit: usize) {
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pub unsafe fn reset_status(dma: pac::dma::Dma, channel_number: u8) {
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let isrn = channel_number as usize / 4;
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let isrbit = channel_number as usize % 4;
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dma.ifcr(isrn).write(|w| {
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w.set_tcif(isrbit, true);
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w.set_teif(isrbit, true);
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