max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

stm32/rcc: add shared code for hsi48 with crs support.

Browse Source
This commit is contained in:
Dario Nieuwenhuis
2023-11-05 23:35:01 +01:00
parent c4a8b79dbc
commit 0272deb158
25 changed files with 136 additions and 161 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
embassy-stm32/src/rcc/h.rs
View File

@ -21,9 +21,6 @@ pub const HSI_FREQ: Hertz = Hertz(64_000_000);
/// CSI speed
pub const CSI_FREQ: Hertz = Hertz(4_000_000);
/// HSI48 speed
pub const HSI48_FREQ: Hertz = Hertz(48_000_000);
const VCO_RANGE: RangeInclusive<Hertz> = Hertz(150_000_000)..=Hertz(420_000_000);
#[cfg(any(stm32h5, pwr_h7rm0455))]
const VCO_WIDE_RANGE: RangeInclusive<Hertz> = Hertz(128_000_000)..=Hertz(560_000_000);
@ -126,7 +123,7 @@ pub struct Config {
pub hsi: Option<HSIPrescaler>,
pub hse: Option<Hse>,
pub csi: bool,
pub hsi48: bool,
pub hsi48: Option<super::Hsi48Config>,
pub sys: Sysclk,
pub pll1: Option<Pll>,
@ -155,7 +152,7 @@ impl Default for Config {
hsi: Some(HSIPrescaler::DIV1),
hse: None,
csi: false,
hsi48: false,
hsi48: Some(Default::default()),
sys: Sysclk::HSI,
pll1: None,
pll2: None,
@ -301,14 +298,7 @@ pub(crate) unsafe fn init(config: Config) {
};
// Configure HSI48.
RCC.cr().modify(|w| w.set_hsi48on(config.hsi48));
let _hsi48 = match config.hsi48 {
false => None,
true => {
while !RCC.cr().read().hsi48rdy() {}
Some(CSI_FREQ)
}
};
let _hsi48 = config.hsi48.map(super::init_hsi48);
// Configure CSI.
RCC.cr().modify(|w| w.set_csion(config.csi));