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stm32/rcc: add shared code for hsi48 with crs support.

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This commit is contained in:
Dario Nieuwenhuis
2023-11-05 23:35:01 +01:00
parent c4a8b79dbc
commit 0272deb158
25 changed files with 136 additions and 161 deletions
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2
examples/stm32h7/src/bin/eth.rs
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@@ -36,7 +36,7 @@ async fn main(spawner: Spawner) -> ! {
use embassy_stm32::rcc::*;
config.rcc.hsi = Some(HSIPrescaler::DIV1);
config.rcc.csi = true;
config.rcc.hsi48 = true; // needed for RNG
config.rcc.hsi48 = Some(Default::default()); // needed for RNG
config.rcc.pll1 = Some(Pll {
source: PllSource::HSI,
prediv: PllPreDiv::DIV4,

2
examples/stm32h7/src/bin/eth_client.rs
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@@ -37,7 +37,7 @@ async fn main(spawner: Spawner) -> ! {
use embassy_stm32::rcc::*;
config.rcc.hsi = Some(HSIPrescaler::DIV1);
config.rcc.csi = true;
config.rcc.hsi48 = true; // needed for RNG
config.rcc.hsi48 = Some(Default::default()); // needed for RNG
config.rcc.pll1 = Some(Pll {
source: PllSource::HSI,
prediv: PllPreDiv::DIV4,

1
examples/stm32h7/src/bin/low_level_timer_api.rs
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@@ -19,7 +19,6 @@ async fn main(_spawner: Spawner) {
use embassy_stm32::rcc::*;
config.rcc.hsi = Some(HSIPrescaler::DIV1);
config.rcc.csi = true;
config.rcc.hsi48 = true; // needed for RNG
config.rcc.pll1 = Some(Pll {
source: PllSource::HSI,
prediv: PllPreDiv::DIV4,

2
examples/stm32h7/src/bin/rng.rs
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@@ -15,7 +15,7 @@ bind_interrupts!(struct Irqs {
#[embassy_executor::main]
async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.hsi48 = true; // needed for RNG.
config.rcc.hsi48 = Some(Default::default()); // needed for RNG
let p = embassy_stm32::init(config);
info!("Hello World!");

2
examples/stm32h7/src/bin/usb_serial.rs
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@@ -25,7 +25,7 @@ async fn main(_spawner: Spawner) {
use embassy_stm32::rcc::*;
config.rcc.hsi = Some(HSIPrescaler::DIV1);
config.rcc.csi = true;
config.rcc.hsi48 = true; // needed for USB
config.rcc.hsi48 = Some(Hsi48Config { sync_from_usb: true }); // needed for USB
config.rcc.pll1 = Some(Pll {
source: PllSource::HSI,
prediv: PllPreDiv::DIV4,