Add external LoRa physical layer functionality.
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@ -197,7 +197,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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/// Useful for on chip peripherals like SUBGHZ which are hardwired.
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/// The bus can optionally be exposed externally with `Spi::new()` still.
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#[allow(dead_code)]
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pub(crate) fn new_internal(
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pub fn new_subghz(
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peri: impl Peripheral<P = T> + 'd,
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txdma: impl Peripheral<P = Tx> + 'd,
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rxdma: impl Peripheral<P = Rx> + 'd,
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